From: Tien Fong Chee tien.fong.chee@intel.com
This version mainly resolved comments from Simon in [v12].
This series is working on top of u-boot.git http://git.denx.de/u-boot.git
[v12]: https://patchwork.ozlabs.org/cover/1058282/ [v11]: https://www.mail-archive.com/u-boot@lists.denx.de/msg318174.html [v10]: https://www.mail-archive.com/u-boot@lists.denx.de/msg318167.html [v9]: https://www.mail-archive.com/u-boot@lists.denx.de/msg316086.html [v8]: https://www.mail-archive.com/u-boot@lists.denx.de/msg316086.html [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.html
Tien Fong Chee (9): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK ARM: socfpga: Cleaning up and ensuring consistent format messages in driver ARM: socfpga: Moving the watchdog reset to the for-loop status polling ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK spl : socfpga: Implement fpga bitstream loading with socfpga loadfs ARM: socfpga: Synchronize the configuration for A10 SoCDK ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 + .../include/mach/fpga_manager_arria10.h | 40 +- arch/arm/mach-socfpga/spl_a10.c | 31 +- board/altera/arria10-socdk/fit_spl_fpga.its | 38 ++ configs/socfpga_arria10_defconfig | 23 +- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +- drivers/fpga/socfpga_arria10.c | 514 ++++++++++++++++++++- include/configs/socfpga_arria10_socdk.h | 5 +- include/image.h | 4 + 9 files changed, 668 insertions(+), 30 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its