Add initial clock driver Allwinner A23.
Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a23.c | 112 ++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a23.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 1f44fed2b9..5f65c9ed44 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -29,6 +29,13 @@ config CLK_SUN6I_A31 This enables common clock driver support for platforms based on Allwinner A31/A31s SoC.
+config CLK_SUN8I_A23 + bool "Clock driver for Allwinner A23" + default MACH_SUN8I_A23 + help + This enables common clock driver support for platforms based + on Allwinner A23 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index e19aee9bf2..8390602746 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o +obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c new file mode 100644 index 0000000000..71f7447ea3 --- /dev/null +++ b/drivers/clk/sunxi/clk_a23.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> + +struct a23_clk_priv { + void *base; +}; + +static int a23_clk_enable(struct clk *clk) +{ + struct a23_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + setbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI: + setbits_le32(priv->base + 0x60, BIT(26)); + return 0; + case CLK_BUS_OHCI: + setbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI: + setbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a23_clk_disable(struct clk *clk) +{ + struct a23_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + clrbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI: + clrbits_le32(priv->base + 0x60, BIT(26)); + return 0; + case CLK_BUS_OHCI: + clrbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI: + clrbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a23_clk_ops = { + .enable = a23_clk_enable, + .disable = a23_clk_disable, +}; + +static int a23_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a23_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a23_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a23_clk_ids[] = { + { .compatible = "allwinner,sun8i-a23-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_a23) = { + .name = "sun8i_a23_ccu", + .id = UCLASS_CLK, + .of_match = a23_clk_ids, + .priv_auto_alloc_size = sizeof(struct a23_clk_priv), + .ofdata_to_platdata = a23_clk_ofdata_to_platdata, + .ops = &a23_clk_ops, + .probe = a23_clk_probe, + .bind = sunxi_clk_bind, +};