Sec proxy data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge.
The backing memory for sec_proxy is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward.
The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done.
So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this).
This allows us to scale and introduce ABI changes back also work with other boot stages that may have left data in the internal memory.
While at this, drop the unused accessor function.
Fixes: f9aa41023bd9 ("mailbox: Introduce K3 Secure Proxy Driver") Signed-off-by: Nishanth Menon nm@ti.com --- drivers/mailbox/k3-sec-proxy.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index a862e55bc391..815808498f2e 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -94,11 +94,6 @@ static inline u32 sp_readl(void __iomem *addr, unsigned int offset) return readl(addr + offset); }
-static inline void sp_writel(void __iomem *addr, unsigned int offset, u32 data) -{ - writel(data, addr + offset); -} - /** * k3_sec_proxy_of_xlate() - Translation of phandle to channel * @chan: Mailbox channel @@ -241,15 +236,20 @@ static int k3_sec_proxy_send(struct mbox_chan *chan, const void *data) /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); writel(data_trail, data_reg); - data_reg++; + data_reg += sizeof(u32); }
/* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= (spt->data + spm->desc->data_end_offset)) - sp_writel(spt->data, spm->desc->data_end_offset, 0); + while (data_reg <= (spt->data + spm->desc->data_end_offset)) { + writel(0x0, data_reg); + data_reg += sizeof(u32); + }
debug("%s: Message successfully sent on thread %ld\n", __func__, chan->id);