Dear Wolfgang,
On Friday 29 July 2011 06:03 PM, Wolfgang Denk wrote:
Dear Aneesh,
In message4E3161ED.5030109@keymile.com Holger Brunck wrote:
today I did a rebase of my development branch to current u-boot master. And I saw on our km_kirkwood board that our egiga0 interface isn't working anymore.
The CPU is a: SoC: Kirkwood 88F6281_A0
After bisecting the current tree I got:
c2dd0d45540397704de9b13287417d21049d34c6 is the first bad commit commit c2dd0d45540397704de9b13287417d21049d34c6 Author: Aneesh Vaneesh@ti.com Date: Thu Jun 16 23:30:49 2011 +0000
armv7: integrate cache maintenance supportAnd indeed after reverting this commit on current HEAD my board is usable again.
The same is true for iMX27 (and probably other boards / SoCs):
I verified for both the "imx27lite" and "magnesium" boards that above patch breaks Ethernet on these iMX27 boards.
Seems we have a bigger problem here...
I had written a small write-up on this earlier today in the below thread: http://marc.info/?l=u-boot&m=131193466800729&w=2
I had done extensive testing on the armv7 cache-maintenance APIs by creating coherency issues and solving them using the APIs. I believe the problems are due to the APIs not being appropriately used where they need to be used, also coupled with the fact that dcache_enable() is now called from board_init_r().
Anyway, I will test my APIs once again on Cortex-A8 and Cortex-A9.
Maybe, I should also write a README with guidelines for correct cache usage.
Also, I would suggest the following to solve the problem with breaking boards: 1. Allow boards to define CONFIG_SYS_DCACHE_OFF and/or 2. Instead of calling dcache_enable() from board_init_r() let's call a new function like dcache_init(). The default implementation of this function shall do nothing. The real implementation in platform code may enable or disable d_cache() on a per SoC/board basis.
best regards, Aneesh