On Aug 27, 2009, at 3:53 PM, Kim Phillips wrote:
On Thu, 27 Aug 2009 08:20:35 +0200 Heiko Schocher hs@denx.de wrote:
MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).
Signed-off-by: Heiko Schocher hs@denx.de
changes since v1:
- added comment from DaveLiu. moved LCRR setting to
cpu_init_r()
changes since v2:
- added comment from Kim Phillips changed LCRR_MASK to 0x7fffffff use clrsetbits()
Heiko - let's go with the SCCR approach of setting bits in the LCRR, and have board config files only specify values for fields they're modifying from the reset value for their processor (this can be extended to 85xx-world).
Did you guys ever come to resolution on this? Realizing we have same issue on 85xx & 86xx (we dont actually set LCRR at all in cpu/ code for 85xx or 86xx.)
- k