From: Stephen Warren swarren@nvidia.com
OUT_CLK_SOURCE_ are currently named after the number of bits the mask they represent includes. However, bit count is not the only possible variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to more completely describe exactly what they represent, without having to go look up the definitions.
Signed-off-by: Stephen Warren swarren@nvidia.com Reviewed-by: Thierry Reding treding@nvidia.com Tested-by: Thierry Reding treding@nvidia.com Acked-by: Thierry Reding treding@nvidia.com --- arch/arm/cpu/tegra-common/clock.c | 16 ++++++++-------- arch/arm/include/asm/arch-tegra/clk_rst.h | 9 +++++---- 2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb912b502..d9f2c767d5d1 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
value = readl(reg);
- value &= ~OUT_CLK_SOURCE_MASK; - value |= source << OUT_CLK_SOURCE_SHIFT; + value &= ~OUT_CLK_SOURCE_31_30_MASK; + value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
value &= ~OUT_CLK_DIVISOR_MASK; value |= divisor << OUT_CLK_DIVISOR_SHIFT; @@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) { u32 *reg = get_periph_source_reg(periph_id);
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); }
/** @@ -305,11 +305,11 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, if (source < 0) return -1; if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); } else { - clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); } udelay(2); return 0; diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bca0b4f..9f81237d2865 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -233,11 +233,12 @@ enum { #define OUT_CLK_DIVISOR_SHIFT 0 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
-#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE_31_30_SHIFT 30 +#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
-#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) +/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ +#define OUT_CLK_SOURCE_31_28_SHIFT 28 +#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ #define SCLK_SYS_STATE_SHIFT 28U