Hi Simon,
On Mon, Nov 25, 2019 at 12:12 PM Simon Glass sjg@chromium.org wrote:
This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v5: None Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Tidy up header guards
- use GENMASK() for VTBAR_MASK
Changes in v3: None Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 + arch/x86/cpu/apollolake/systemagent.c | 19 ++++++++++ .../include/asm/arch-apollolake/systemagent.h | 37 +++++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index fdda748ea3..3a8c2f66a3 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,5 +2,7 @@ # # Copyright 2019 Google LLC
+obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c new file mode 100644 index 0000000000..3a41b329c3 --- /dev/null +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2017 Intel Corporation.
- Take from coreboot project file of the same name
- */
+#include <common.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/arch/systemagent.h>
+void enable_bios_reset_cpl(void) +{
/** Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU* that BIOS has initialised memory and power management*/
Is this absolutely necessary? What happens if we don't do this? Or does FSP-S do such for us?
setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);+} diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h new file mode 100644 index 0000000000..206d8903fa --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/systemagent.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2017 Intel Corporation.
- Take from coreboot project file of the same name
- */
+#ifndef _ASM_ARCH_SYSTEMAGENT_H +#define _ASM_ARCH_SYSTEMAGENT_H
+/* Device 0:0.0 PCI configuration space */ +#define MCHBAR 0x48
+/* RAPL Package Power Limit register under MCHBAR */ +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 +#define BIOS_RESET_CPL 0x7078 +#define PCODE_INIT_DONE BIT(8) +#define MCHBAR_RAPL_PPL 0x70A8 +#define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE BIT(23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK GENMASK_ULL(39, 12) +#define VTBAR_SIZE 0x1000
+/**
- enable_bios_reset_cpl() - Tell the system agent that memory/power are ready
- This should be called when U-Boot has set up the memory and power
- management.
- */
+void enable_bios_reset_cpl(void);
+#endif
Regards, Bin