From: Chee Hong Ang chee.hong.ang@intel.com
Allow MMC driver to access System Manager's SDMMC control register in non- secure mode (EL2).
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
drivers/mmc/socfpga_dw_mmc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 786cdc7..558f246 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -5,6 +5,7 @@
#include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/secure_reg_helper.h> #include <asm/arch/system_manager.h> #include <clk.h> #include <dm.h> @@ -57,10 +58,12 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel);
- writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
socfpga_secure_reg_write32(sdmmc_mask, socfpga_get_sysmgr_addr()
SYSMGR_SDMMC);debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +SYSMGR_SDMMC));/* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
-- 2.7.4
This SDMMC driver need to access System Manager's SDMMC control register (secure zone) to configure the clock's phase shift settings. I don't think this could be separated from the driver. I will add/define a high-level API in ATF to be used by this SDMMC driver from non-secure world (EL2). This high-level API (SMC/PSCI calls) will be properly documented in 'include/linux/intel-smc.h'