Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage.
Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- board/freescale/p2041rdb/eth.c | 39 ------------------------------- board/freescale/p2041rdb/p2041rdb.c | 44 +++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 39 deletions(-)
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index fec9777..4b0d577 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -136,11 +136,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } #endif /* #ifdef CONFIG_FMAN_ENET */
-#define CPLD_LANE_A_SEL 0x1 -#define CPLD_LANE_G_SEL 0x2 -#define CPLD_LANE_C_SEL 0x4 -#define CPLD_LANE_D_SEL 0x8 - int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET @@ -148,10 +143,6 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - u8 mux = CPLD_READ(serdes_mux);
printf("Initializing Fman\n");
@@ -181,36 +172,6 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL); - switch (srds_prtcl) { - case 0x2: - case 0xf: - mux &= ~CPLD_LANE_G_SEL; - break; - case 0x5: - case 0x9: - case 0xa: - case 0x17: - mux |= CPLD_LANE_G_SEL; - break; - case 0x14: - mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL; - break; - case 0x8: - case 0x16: - case 0x19: - case 0x1a: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; - break; - case 0x1c: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; - break; - default: - printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - CPLD_WRITE(serdes_mux, mux); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1;
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 51c4310..3bda09c 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -105,6 +105,49 @@ int board_early_init_f(void) return 0; }
+#define CPLD_LANE_A_SEL 0x1 +#define CPLD_LANE_G_SEL 0x2 +#define CPLD_LANE_C_SEL 0x4 +#define CPLD_LANE_D_SEL 0x8 + +void board_config_lanes_mux(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + u8 mux = 0; + switch (srds_prtcl) { + case 0x2: + case 0x5: + case 0x9: + case 0xa: + case 0xf: + break; + case 0x8: + mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x14: + mux |= CPLD_LANE_A_SEL; + break; + case 0x17: + mux |= CPLD_LANE_G_SEL; + break; + case 0x16: + case 0x19: + case 0x1a: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x1c: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; + break; + default: + printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + CPLD_WRITE(serdes_mux, mux); +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -128,6 +171,7 @@ int board_early_init_r(void)
set_liodns(); setup_portals(); + board_config_lanes_mux();
return 0; }