The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang Haijun.Zhang@freescale.com --- drivers/mmc/fsl_esdhc.c | 6 ++++++ include/configs/T4240QDS.h | 2 ++ 2 files changed, 8 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e330379..524cc10 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -593,6 +593,12 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->host_caps &= ~MMC_MODE_4BIT; }
+ /* Detect if the upper 4 pins are used for ESDHC */ +#if defined(CONFIG_T4240QDS) + if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) + mmc->host_caps &= ~MMC_MODE_8BIT; +#endif + if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 3777ccb..77e8ac0 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC_WIDTH8 1 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)