Dear HeungJun, Kim,
On 6 January 2012 21:55, HeungJun, Kim riverful.kim@samsung.com wrote:
This patch adds support for Samsung TRATS board
Signed-off-by: HeungJun, Kim riverful.kim@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com
MAINTAINERS | 4 + board/samsung/trats/Makefile | 45 ++ board/samsung/trats/lowlevel_init.S | 50 +++ board/samsung/trats/lowlevel_util.c | 137 ++++++ board/samsung/trats/trats.c | 250 +++++++++++ board/samsung/trats/trats_setup.h | 812 +++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/trats.h | 216 ++++++++++ 8 files changed, 1515 insertions(+), 0 deletions(-) create mode 100644 board/samsung/trats/Makefile create mode 100644 board/samsung/trats/lowlevel_init.S create mode 100644 board/samsung/trats/lowlevel_util.c create mode 100644 board/samsung/trats/trats.c create mode 100644 board/samsung/trats/trats_setup.h create mode 100644 include/configs/trats.h
diff --git a/board/samsung/trats/lowlevel_init.S b/board/samsung/trats/lowlevel_init.S new file mode 100644 index 0000000..9159063 --- /dev/null +++ b/board/samsung/trats/lowlevel_init.S @@ -0,0 +1,50 @@ +/*
- Lowlevel setup for TRATS board based on EXYNOS4210
- Copyright (C) 2011 Samsung Electronics
- Heungjun Kim riverful.kim@samsung.com
- Kyungmin Park kyungmin.park@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include "trats_setup.h"
- .globl pmu_init
- .globl uart_init
- .globl watchdog_disable
- .globl clock_init
- .globl pmic_reset
- .globl lowlevel_init
+lowlevel_init:
- push {lr}
- bl pmic_reset @ PMIC reset
- bl clock_init @ Init Clock
- bl watchdog_disable @ Disable Watchdog
- bl uart_init @ Init UART
- bl pmu_init @ Init PMU
- pop {pc}
- nop
diff --git a/board/samsung/trats/lowlevel_util.c b/board/samsung/trats/lowlevel_util.c new file mode 100644 index 0000000..d67a095 --- /dev/null +++ b/board/samsung/trats/lowlevel_util.c @@ -0,0 +1,137 @@ +/*
- Copyright (C) 2011 Samsung Electronics
- Heungjun Kim riverful.kim@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include "trats_setup.h"
+void pmic_reset(void) +{
- u32 base = EXYNOS4_GPIO_PART2_BASE;
- u32 gpio;
- gpio = readl(base + EXYNOS4_GPIO_X2_CON_OFFSET);
- gpio &= ~EXYNOS4_GPIO_X2_CON_MASK;
- gpio |= EXYNOS4_GPIO_X2_CON_VAL;
- writel(EXYNOS4_GPIO_X2_CON_VAL, base + EXYNOS4_GPIO_X2_CON_OFFSET);
- gpio = readl(base + EXYNOS4_GPIO_X2_DAT_OFFSET);
- gpio |= EXYNOS4_GPIO_X2_DAT_VAL;
- writel(gpio, base + EXYNOS4_GPIO_X2_DAT_OFFSET);
+}
Please use structures instead of defines.
+void clock_init(void) +{
- u32 base = EXYNOS4_CLOCK_BASE;
- writel(CLK_SRC_CPU_VAL, base + CLK_SRC_CPU_OFFSET);
- writel(CLK_DIV_CPU0_VAL, base + CLK_DIV_CPU0_OFFSET);
- writel(CLK_DIV_CPU1_VAL, base + CLK_DIV_CPU1_OFFSET);
- writel(CLK_DIV_DMC0_VAL, base + CLK_DIV_DMC0_OFFSET);
- writel(CLK_DIV_DMC1_VAL, base + CLK_DIV_DMC1_OFFSET);
- writel(CLK_SRC_TOP0_VAL, base + CLK_SRC_TOP0_OFFSET);
- writel(CLK_SRC_FSYS_VAL, base + CLK_SRC_FSYS_OFFSET);
- writel(CLK_SRC_PERIL0_VAL, base + CLK_SRC_PERIL0_OFFSET);
- writel(CLK_DIV_LEFTBUS_VAL, base + CLK_DIV_LEFTBUS_OFFSET);
- writel(CLK_DIV_RIGHTBUS_VAL, base + CLK_DIV_RIGHTBUS_OFFSET);
- writel(CLK_DIV_TOP_VAL, base + CLK_DIV_TOP_OFFSET);
- writel(CLK_DIV_FSYS1_VAL, base + CLK_DIV_FSYS1_OFFSET);
- writel(CLK_DIV_FSYS2_VAL, base + CLK_DIV_FSYS2_OFFSET);
- writel(CLK_DIV_FSYS3_VAL, base + CLK_DIV_FSYS3_OFFSET);
- writel(CLK_DIV_PERIL0_VAL, base + CLK_DIV_PERIL0_OFFSET);
- /* PLL Setting */
- writel(PLL_LOCKTIME, base + APLL_LOCK_OFFSET);
- writel(PLL_LOCKTIME, base + MPLL_LOCK_OFFSET);
- writel(PLL_LOCKTIME, base + EPLL_LOCK_OFFSET);
- writel(PLL_LOCKTIME, base + VPLL_LOCK_OFFSET);
- writel(APLL_CON1_VAL, base + APLL_CON1_OFFSET);
- writel(APLL_CON0_VAL, base + APLL_CON0_OFFSET);
- writel(MPLL_CON1_VAL, base + MPLL_CON1_OFFSET);
- writel(MPLL_CON0_VAL, base + MPLL_CON0_OFFSET);
- writel(EPLL_CON1_VAL, base + EPLL_CON1_OFFSET);
- writel(EPLL_CON0_VAL, base + EPLL_CON0_OFFSET);
- writel(VPLL_CON1_VAL, base + VPLL_CON1_OFFSET);
- writel(VPLL_CON0_VAL, base + VPLL_CON0_OFFSET);
- /* Clock Gating */
- writel(CLK_GATE_IP_CAM_VAL, base + CLK_GATE_IP_CAM_OFFSET);
- writel(CLK_GATE_IP_VP_VAL, base + CLK_GATE_IP_VP_OFFSET);
- writel(CLK_GATE_IP_MFC_VAL, base + CLK_GATE_IP_MFC_OFFSET);
- writel(CLK_GATE_IP_G3D_VAL, base + CLK_GATE_IP_G3D_OFFSET);
- writel(CLK_GATE_IP_IMAGE_VAL, base + CLK_GATE_IP_IMAGE_OFFSET);
- writel(CLK_GATE_IP_LCD0_VAL, base + CLK_GATE_IP_LCD0_OFFSET);
- writel(CLK_GATE_IP_LCD1_VAL, base + CLK_GATE_IP_LCD1_OFFSET);
- writel(CLK_GATE_IP_FSYS_VAL, base + CLK_GATE_IP_FSYS_OFFSET);
- writel(CLK_GATE_IP_GPS_VAL, base + CLK_GATE_IP_GPS_OFFSET);
- writel(CLK_GATE_IP_PERIL_VAL, base + CLK_GATE_IP_PERIL_OFFSET);
- writel(CLK_GATE_IP_PERIR_VAL, base + CLK_GATE_IP_PERIR_OFFSET);
- writel(CLK_GATE_BLOCK_VAL, base + CLK_GATE_BLOCK_OFFSET);
+}
ditto.
+void watchdog_disable(void) +{
- u32 base = EXYNOS4_WATCHDOG_BASE;
- writel(0, base);
+}
+void uart_init(void) +{
- u32 base = EXYNOS4_GPIO_PART1_BASE;
- writel(EXYNOS4_GPIO_A0_CON_VAL, base + EXYNOS4_GPIO_A0_CON_OFFSET);
- writel(EXYNOS4_GPIO_A1_CON_VAL, base + EXYNOS4_GPIO_A1_CON_OFFSET);
- /* UART_SEL */
- base = EXYNOS4_GPIO_PART2_BASE;
- writel(EXYNOS4_GPIO_Y4_CON_VAL, base + EXYNOS4_GPIO_Y4_CON_OFFSET);
- writel(EXYNOS4_GPIO_Y4_PUD_VAL, base + EXYNOS4_GPIO_Y4_PUD_OFFSET);
- writel(EXYNOS4_GPIO_Y4_DAT_VAL, base + EXYNOS4_GPIO_Y4_DAT_OFFSET);
ditto.
- base = EXYNOS4_UART_BASE;
- base += EXYNOS4_DEFAULT_UART_OFFSET;
- writel(ULCON_VAL, base + ULCON_OFFSET);
- writel(UCON_VAL, base + UCON_OFFSET);
- writel(UFCON_VAL, base + UFCON_OFFSET);
- writel(UBRDIV_VAL, base + UBRDIV_OFFSET);
- writel(UFRACVAL_VAL, base + UFRACVAL_OFFSET);
Actually, we don't need this. It's duplicated setting. Please remove it.
+}
+void pmu_init(void) +{
- u32 base = EXYNOS4_POWER_BASE;
- /* PS HOLD */
- base += EXYNOS4_PS_HOLD_CON_OFFSET;
- writel(EXYNOS4_PS_HOLD_CON_VAL, base);
- /* Set power down */
- base += POWER_DOWN_OFFSET;
- writel(0, base + POWER_TV_CONFIGURATION_OFFSET);
- writel(0, base + POWER_MFC_CONFIGURATION_OFFSET);
- writel(0, base + POWER_G3D_CONFIGURATION_OFFSET);
- writel(0, base + POWER_LCD_CONFIGURATION_OFFSET);
- writel(0, base + POWER_GPS_CONFIGURATION_OFFSET);
Please use structures instead of defines.
+} diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c new file mode 100644 index 0000000..640108d --- /dev/null +++ b/board/samsung/trats/trats.c @@ -0,0 +1,250 @@ +/*
- Copyright (C) 2011 Samsung Electronics
- Heungjun Kim riverful.kim@samsung.com
- Kyungmin Park kyungmin.park@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <pmic.h> +#include <usb/s3c_udc.h> +#include <asm/arch/cpu.h> +#include <max8998_pmic.h>
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int board_rev;
+#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{
- return board_rev;
+} +#endif
+static void check_hw_revision(void);
+int board_init(void) +{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- check_hw_revision();
- printf("HW Revision:\t0x%x\n", board_rev);
+#if defined(CONFIG_PMIC)
- pmic_init();
+#endif
- return 0;
+}
+int dram_init(void) +{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
- return 0;
+}
+void dram_init_banksize(void) +{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+static unsigned int get_hw_revision(void) +{
- struct exynos4_gpio_part1 *gpio;
- int hwrev = 0;
- int i;
- gpio = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- /* hw_rev[3:0] == GPE1[3:0] */
- for (i = 0; i < 4; i++) {
- s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
- s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
- }
- udelay(1);
- for (i = 0; i < 4; i++)
- hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
- debug("hwrev 0x%x\n", hwrev);
- return hwrev;
+}
+static void check_hw_revision(void) +{
- int hwrev;
- hwrev = get_hw_revision();
- board_rev |= hwrev;
+}
+#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{
- puts("Board:\tTRATS\n");
- return 0;
+} +#endif
+#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{
- struct exynos4_gpio_part2 *gpio;
- int i, err;
- gpio = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
- s5p_gpio_direction_output(&gpio->k0, 2, 1);
- s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
- /*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
- }
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
- }
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = s5p_mmc_init(0, 8);
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
- }
- return err;
Please remove this space.
+} +#endif
+#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{
- int ret = 0;
- struct pmic *p = get_pmic();
- if (pmic_probe(p))
- return -1;
- if (on) {
- ret |= pmic_set_output(p,
- MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
- MAX8998_SAFEOUT1, LDO_ON);
- ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_ON);
- ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_ON);
- } else {
- ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_OFF);
- ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_OFF);
- ret |= pmic_set_output(p,
- MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
- MAX8998_SAFEOUT1, LDO_OFF);
- }
- if (ret) {
- puts("MAX8998 LDO setting error!\n");
- return -1;
- }
- return 0;
+}
+struct s3c_plat_otg_data s5pc210_otg_data = {
- .phy_control = s5pc210_phy_control,
- .regs_phy = EXYNOS4_USBPHY_BASE,
- .regs_otg = EXYNOS4_USBOTG_BASE,
- .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
- .usb_flags = PHY0_SLEEP,
+}; +#endif
Thanks. Minkyu Kang.