To sync up with use of a pinctrl-driver and to have individual gpiobank nodes (to easier model controllers that have gaps in the use of bank numbering), this updates the DTS.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/dts/sun50i-a64.dtsi | 73 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 69 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 24406d0..efed838 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -1,697 +1,762 @@ /* * Copyright (C) 2016 ARM Ltd. * based on the Allwinner H3 dtsi: * Copyright (C) 2015 Jens Kuske jenskuske@gmail.com * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/sun4i-a10.h>
/ { interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>;
cpus { #address-cells = <1>; #size-cells = <0>;
cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0>; enable-method = "psci"; };
cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <1>; enable-method = "psci"; };
cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <2>; enable-method = "psci"; };
cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <3>; enable-method = "psci"; }; };
psci { compatible = "arm,psci-0.2"; method = "smc"; };
memory { device_type = "memory"; reg = <0x40000000 0>; };
gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; interrupt-controller; #interrupt-cells = <3>; #address-cells = <0>;
reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
clocks { #address-cells = <1>; #size-cells = <1>; ranges;
osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; };
osc32k: osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; };
pll1: pll1_clk@1c20000 { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; };
pll6: pll6_clk@1c20028 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6", "pll6x2"; };
pll6d2: pll6d2_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <2>; clock-mult = <1>; clocks = <&pll6 0>; clock-output-names = "pll6d2"; };
pll7: pll7_clk@1c2002c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-pll6-clk"; reg = <0x01c2002c 0x4>; clocks = <&osc24M>; clock-output-names = "pll7", "pll7x2"; };
cpu: cpu_clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20050 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; clock-output-names = "cpu"; critical-clocks = <0>; };
axi: axi_clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20050 0x4>; clocks = <&cpu>; clock-output-names = "axi"; };
ahb1: ahb1_clk@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun6i-a31-ahb1-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; clock-output-names = "ahb1"; };
ahb2: ahb2_clk@1c2005c { #clock-cells = <0>; compatible = "allwinner,sun8i-h3-ahb2-clk"; reg = <0x01c2005c 0x4>; clocks = <&ahb1>, <&pll6d2>; clock-output-names = "ahb2"; };
apb1: apb1_clk@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1>; clock-output-names = "apb1"; };
apb2: apb2_clk@1c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>; clock-output-names = "apb2"; };
bus_gates: bus_gates_clk@1c20060 { #clock-cells = <1>; compatible = "allwinner,sun50i-a64-bus-gates-clk", "allwinner,sunxi-multi-bus-gates-clk"; reg = <0x01c20060 0x14>; ahb1_parent { clocks = <&ahb1>; clock-indices = <1>, <5>, <6>, <8>, <9>, <10>, <13>, <14>, <18>, <19>, <20>, <21>, <23>, <24>, <25>, <28>, <32>, <35>, <36>, <37>, <40>, <43>, <44>, <52>, <53>, <54>, <135>; clock-output-names = "bus_mipidsi", "bus_ce", "bus_dma", "bus_mmc0", "bus_mmc1", "bus_mmc2", "bus_nand", "bus_sdram", "bus_ts", "bus_hstimer", "bus_spi0", "bus_spi1", "bus_otg", "bus_otg_ehci0", "bus_ehci0", "bus_otg_ohci0", "bus_ve", "bus_lcd0", "bus_lcd1", "bus_deint", "bus_csi", "bus_hdmi", "bus_de", "bus_gpu", "bus_msgbox", "bus_spinlock", "bus_dbg"; }; ahb2_parent { clocks = <&ahb2>; clock-indices = <17>, <29>; clock-output-names = "bus_gmac", "bus_ohci0"; }; apb1_parent { clocks = <&apb1>; clock-indices = <64>, <65>, <69>, <72>, <76>, <77>, <78>; clock-output-names = "bus_codec", "bus_spdif", "bus_pio", "bus_ths", "bus_i2s0", "bus_i2s1", "bus_i2s2"; }; abp2_parent { clocks = <&apb2>; clock-indices = <96>, <97>, <98>, <101>, <112>, <113>, <114>, <115>, <116>; clock-output-names = "bus_i2c0", "bus_i2c1", "bus_i2c2", "bus_scr", "bus_uart0", "bus_uart1", "bus_uart2", "bus_uart3", "bus_uart4"; }; };
mmc0_clk: mmc0_clk@1c20088 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; clock-output-names = "mmc0"; };
mmc1_clk: mmc1_clk@1c2008c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; clock-output-names = "mmc1"; };
mmc2_clk: mmc2_clk@1c20090 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; clock-output-names = "mmc2"; }; };
soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges;
mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc", "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&bus_gates 8>, <&mmc0_clk>, <&mmc0_clk>, <&mmc0_clk>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&ahb_rst 8>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
mmc1: mmc@1c10000 { compatible = "allwinner,sun50i-a64-mmc", "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; clocks = <&bus_gates 9>, <&mmc1_clk>, <&mmc1_clk>, <&mmc1_clk>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&ahb_rst 9>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
mmc2: mmc@1c11000 { compatible = "allwinner,sun50i-a64-mmc", "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; clocks = <&bus_gates 10>, <&mmc2_clk>, <&mmc2_clk>, <&mmc2_clk>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&ahb_rst 10>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
pio: pinctrl@1c20800 { compatible = "allwinner,sun50i-a64-pinctrl"; reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bus_gates 69>; + gpio-controller; #gpio-cells = <3>; + interrupt-controller; #interrupt-cells = <2>;
- uart0_pins_a: uart0@0 { + #address-cells = <1>; + #size-cells = <1>; + + /* The A64 does not have bank A and leaves a hole in the + address space where it normally would be */ + + gpiob: gpiob@24 { + compatible = "allwinner,sunxi-gpiobank"; + allwinner,gpiobank-name = <'B'>; + reg = < 0x24 0x24 >, < 0x200 0x1c >; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpioc: gpioc@48 { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0x48 0x24 >; + allwinner,gpiobank-name = <'C'>; + }; + + gpiod: gpiod@6c { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0x6c 0x24 >; + allwinner,gpiobank-name = <'D'>; + }; + + gpioe: gpioe@90 { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0x90 0x24 >; + allwinner,gpiobank-name = <'E'>; + }; + + gpiof: gpiof@b4 { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0xb4 0x24 >; + allwinner,gpiobank-name = <'F'>; + }; + + gpiog: gpiog@d8 { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0xd8 0x24 >, < 0x220 0x1c >; + allwinner,gpiobank-name = <'G'>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpioh: gpioh@fc { + compatible = "allwinner,sunxi-gpiobank"; + reg = < 0xfc 0x24 >, < 0x220 0x1c >; + allwinner,gpiobank-name = <'H'>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0_pins_a: uart0_pins_a { allwinner,pins = "PB8", "PB9"; allwinner,function = "uart0"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart0_pins_b: uart0@1 { allwinner,pins = "PF2", "PF3"; allwinner,function = "uart0"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart1_2pins: uart1_2@0 { allwinner,pins = "PG6", "PG7"; allwinner,function = "uart1"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart1_4pins: uart1_4@0 { allwinner,pins = "PG6", "PG7", "PG8", "PG9"; allwinner,function = "uart1"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart2_2pins: uart2_2@0 { allwinner,pins = "PB0", "PB1"; allwinner,function = "uart2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart2_4pins: uart2_4@0 { allwinner,pins = "PB0", "PB1", "PB2", "PB3"; allwinner,function = "uart2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart3_pins_a: uart3@0 { allwinner,pins = "PD0", "PD1"; allwinner,function = "uart3"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart3_2pins_b: uart3_2@1 { allwinner,pins = "PH4", "PH5"; allwinner,function = "uart3"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart3_4pins_b: uart3_4@1 { allwinner,pins = "PH4", "PH5", "PH6", "PH7"; allwinner,function = "uart3"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart4_2pins: uart4_2@0 { allwinner,pins = "PD2", "PD3"; allwinner,function = "uart4"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
uart4_4pins: uart4_4@0 { allwinner,pins = "PD2", "PD3", "PD4", "PD5"; allwinner,function = "uart4"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
mmc0_pins: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,function = "mmc0"; allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
mmc0_default_cd_pin: mmc0_cd_pin@0 { allwinner,pins = "PF6"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; };
mmc1_pins: mmc1@0 { allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; allwinner,function = "mmc1"; allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
mmc2_pins: mmc2@0 { allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10"; allwinner,function = "mmc2"; allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
i2c0_pins: i2c0_pins { allwinner,pins = "PH0", "PH1"; allwinner,function = "i2c0"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
i2c1_pins: i2c1_pins { allwinner,pins = "PH2", "PH3"; allwinner,function = "i2c1"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
i2c2_pins: i2c2_pins { allwinner,pins = "PE14", "PE15"; allwinner,function = "i2c2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
rmii_pins: rmii_pins { allwinner,pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; allwinner,function = "emac"; allwinner,drive = <SUN4I_PINCTRL_40_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; };
rgmii_pins: rgmii_pins { allwinner,pins = "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23"; allwinner,function = "emac"; allwinner,drive = <SUN4I_PINCTRL_40_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; };
r_pio: pinctrl@01f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #size-cells = <0>; #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + gpiol: gpiol@0 { + compatible = "allwinner,sunxi-gpiobank"; + allwinner,gpiobank-name = <'L'>; + reg = < 0x0 0x24 >, < 0x200 0x1c >; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + }; };
ahb_rst: reset@1c202c0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202c0 0xc>; };
apb1_rst: reset@1c202d0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202d0 0x4>; };
apb2_rst: reset@1c202d8 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202d8 0x4>; };
uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 112>; resets = <&apb2_rst 16>; status = "disabled"; };
uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 113>; resets = <&apb2_rst 17>; status = "disabled"; };
uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 114>; resets = <&apb2_rst 18>; status = "disabled"; };
uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 115>; resets = <&apb2_rst 19>; status = "disabled"; };
uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 116>; resets = <&apb2_rst 20>; status = "disabled"; };
rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; };
i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bus_gates 96>; resets = <&apb2_rst 0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bus_gates 97>; resets = <&apb2_rst 1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bus_gates 98>; resets = <&apb2_rst 2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
emac: ethernet@01c30000 { compatible = "allwinner,sun50i-a64-emac"; reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; reg-names = "emac", "syscon"; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; resets = <&ahb_rst 17>; reset-names = "ahb"; clocks = <&bus_gates 17>; clock-names = "ahb"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; };
usbphy: phy@1c1b810 { compatible = "allwinner,sun50i-a64-usb-phy", "allwinner,sun8i-a33-usb-phy"; reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>; reg-names = "phy_ctrl", "pmu1"; status = "disabled"; #phy-cells = <1>; };
ehci1: usb@01c1b000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; };
ohci1: usb@01c1b400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy 1>; phy-names = "usb"; status = "enabled"; }; }; };