[U-Boot] [PATCH 08/21] ARM: uniphier: add a field to specify DDR3+

26 Feb 2016

Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
---
arch/arm/mach-uniphier/boards.c               |  2 ++
 arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c  |  5 +++--
 arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c |  5 +++--
 arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c |  9 +++------
 arch/arm/mach-uniphier/dram/ddrphy-regs.h     | 10 +++++++---
 arch/arm/mach-uniphier/dram/umc-ph1-ld4.c     |  9 +++++----
 arch/arm/mach-uniphier/dram/umc-ph1-pro4.c    | 12 ++++++++----
 arch/arm/mach-uniphier/dram/umc-ph1-sld8.c    | 24 ++++++++++--------------
 arch/arm/mach-uniphier/init.h                 |  3 +++
 9 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 05b7c76..408aff0 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -38,6 +38,7 @@ static const struct uniphier_board_data ph1_sld3_data = {
 static const struct uniphier_board_data ph1_ld4_data = {
    .dram_freq = 1600,
    .dram_nr_ch = 2,
+	.dram_ddr3plus = true,
    .dram_ch[0] = {
    	.base = 0x80000000,
    	.size = 0x10000000,
@@ -89,6 +90,7 @@ static const struct uniphier_board_data ph1_pro4_2g_data = {
 static const struct uniphier_board_data ph1_sld8_data = {
    .dram_freq = 1333,
    .dram_nr_ch = 2,
+	.dram_ddr3plus = true,
    .dram_ch[0] = {
    	.base = 0x80000000,
    	.size = 0x10000000,
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index d2bc5a1..3000a28 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -9,7 +9,8 @@
#include "ddrphy-regs.h"
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			bool ddr3plus)
 {
    u32 tmp;
@@ -61,7 +62,7 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
    else
    	writel(0x00000298, &phy->mr2);
-	writel(0x00000800, &phy->mr3);
+	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
    	;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
index 9fb34f7..b4dca35 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
@@ -9,7 +9,8 @@
#include "ddrphy-regs.h"
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			 bool ddr3plus)
 {
    u32 tmp;
@@ -55,7 +56,7 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
    else
    	writel(0x00000298, &phy->mr2);
-	writel(0x00000000, &phy->mr3);
+	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
    	;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
index 6510690..0d2ae42 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
@@ -10,7 +10,8 @@
#include "ddrphy-regs.h"
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			 bool ddr3plus)
 {
    u32 tmp;
@@ -62,11 +63,7 @@ int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
    else
    	writel(0x00000298, &phy->mr2);
-#ifdef CONFIG_DDR_STANDARD
-	writel(0x00000000, &phy->mr3);
-#else
-	writel(0x00000800, &phy->mr3);
-#endif
+	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
    	;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
index 03aedc2..206fabd 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -11,6 +11,7 @@
#include <linux/bitops.h>
 #include <linux/compiler.h>
+#include <linux/types.h>
#ifndef __ASSEMBLY__
@@ -169,9 +170,12 @@ struct ddrphy {
 #define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			bool ddr3plus);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			 bool ddr3plus);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
+			 bool ddr3plus);
 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
 int ddrphy_training(struct ddrphy __iomem *phy);
 #endif
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 638aa11..957a38f 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -96,7 +96,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
    writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
 }
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 {
    void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
    void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
@@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-	ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
+	ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
    ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-	ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
+	ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
ddrphy_prepare_training(phy1_0, 1);
    ddrphy_training(phy1_0);
@@ -141,7 +141,8 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
        bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
    	return umc_init_sub(bd->dram_freq,
    			    bd->dram_ch[0].size / SZ_128M,
-				    bd->dram_ch[1].size / SZ_128M);
+				    bd->dram_ch[1].size / SZ_128M,
+				    bd->dram_ddr3plus);
    } else {
    	pr_err("Unsupported DDR configuration\n");
    	return -EINVAL;
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index f89b1da..38dd338 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -138,28 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-	ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size);
+	ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
+			     bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
    ddrphy_training(phy0_0);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-	ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size);
+	ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
+			     bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_1, 1);
    ddrphy_training(phy0_1);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-	ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size);
+	ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
+			     bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_0, 0);
    ddrphy_training(phy1_0);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-	ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size);
+	ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
+			     bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_1, 1);
    ddrphy_training(phy1_1);
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index fa0619f..3cbb7ba 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -48,15 +48,10 @@ static void umc_start_ssif(void __iomem *ssif_base)
 }
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
+			      int size, int freq, bool ddr3plus)
 {
-#ifdef CONFIG_DDR_STANDARD
-	writel(0x55990b11, dramcont + UMC_CMDCTLA);
-	writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
-	writel(0x45990b11, dramcont + UMC_CMDCTLA);
-	writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
+	writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA);
+	writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB);
if (size == 1)
    	writel(0x00240512, dramcont + UMC_SPCCTLA);
@@ -85,7 +80,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
    writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
 }
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 {
    void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
    void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
@@ -102,20 +97,20 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-	ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
+	ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
    ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-	ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
+	ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
ddrphy_prepare_training(phy1_0, 1);
    ddrphy_training(phy1_0);
-	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
-	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus);
umc_start_ssif(ssif_base);
@@ -130,7 +125,8 @@ int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
        bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
    	return umc_init_sub(bd->dram_freq,
    			    bd->dram_ch[0].size / SZ_128M,
-				    bd->dram_ch[1].size / SZ_128M);
+				    bd->dram_ch[1].size / SZ_128M,
+				    bd->dram_ddr3plus);
    } else {
    	pr_err("Unsupported DDR configuration\n");
    	return -EINVAL;
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index aabd84a..e969fd0 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -7,6 +7,8 @@
 #ifndef __MACH_INIT_H
 #define __MACH_INIT_H
+#include <linux/types.h>
+
 #define UNIPHIER_MAX_NR_DRAM_CH		3
struct uniphier_dram_ch {
@@ -18,6 +20,7 @@ struct uniphier_dram_ch {
 struct uniphier_board_data {
    unsigned int dram_freq;
    unsigned int dram_nr_ch;
+	bool dram_ddr3plus;
    struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
 };
-- 
1.9.1


    