Texas Instruments has begun enabling security settings on the SoCs it produces to instruct ROM and TIFS to begin protecting the Security Management Subsystem (SMS) from other binaries we load into the chip by default.
One way ROM and TIFS do this is by enabling firewalls to protect the OCSRAM and HSM RAM regions they're using during bootup.
The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect itself from the main domain applications. This means the 'bootindex' value in HSM RAM, left by ROM to indicate if we're using the primary or secondary boot-method, must be moved to OCSRAM (that TIFS has open for us) before we make the jump to the main domain so the main domain's bootloaders can keep access to this information.
Signed-off-by: Bryan Brattlof bb@ti.com --- arch/arm/mach-k3/Kconfig | 4 +++- arch/arm/mach-k3/am62a7_init.c | 16 ++++++++++++++-- arch/arm/mach-k3/include/mach/am62a_hardware.h | 17 ++++++++++++++++- 3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 87da6b49ee6b7..a8c3a593d5704 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -69,7 +69,9 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 - default 0x43c3f290 if SOC_K3_AM625 || SOC_K3_AM62A7 + default 0x43c3f290 if SOC_K3_AM625 + default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R + default 0x7000f290 if SOC_K3_AM62A7 && ARM64 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index e9569f0d26418..02da24a3d6f0d 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -25,8 +25,11 @@ static struct rom_extended_boot_data bootdata __section(".data"); static void store_boot_info_from_rom(void) { bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); - memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, - sizeof(struct rom_extended_boot_data)); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); + } }
static void ctrl_mmr_unlock(void) @@ -123,6 +126,15 @@ void board_init_f(ulong dummy) k3_sysfw_loader(true, NULL, NULL); #endif
+#if defined(CONFIG_CPU_V7R) + /* + * Relocate boot information to OCRAM (after TIFS has opend this + * region for us) so the next bootloader stages can keep access to + * primary vs backup bootmodes. + */ + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); +#endif + /* * Force probe of clk_k3 driver here to ensure basic default clock * configuration is always done. diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index 52b0d9b3cb95c..13bf50f147b1e 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -68,7 +68,22 @@
#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
-/* Use Last 2K as Scratch pad */ +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +/* + * During the boot process ROM will kill anything that writes to OCSRAM. + * This means the wakeup SPL cannot use this region during boot. To + * complicate things, TIFS will set a firewall between HSM RAM and the + * main domain. + * + * So, during the wakeup SPL, we will need to store the EEPROM data + * somewhere in HSM RAM, and the main domain's SPL will need to store it + * somewhere in OCSRAM + */ +#ifdef CONFIG_CPU_V7R +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 +#else #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 +#endif /* CONFIG_CPU_V7R */
#endif /* __ASM_ARCH_AM62A_HARDWARE_H */