Dear Jagannadha,
Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki <at> xilinx.com>
writes:
Hi Andy,
The latest patch "mmc: Properly determine maximum supported bus width" (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) is causing some error status
issue on
zynq platform with MMC Plus cards.
Here the out what I get with inclusion of this patch on u-boot tree. zynq-uboot> mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: 1e OEM: ffff Name: MMC Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 4-bit
When I revert this path, I am unable to see the status error. zynq-uboot> mmcinfo Device: zynq_sdhci Manufacturer ID: 1e OEM: ffff Name: MMC Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 12-bit
I think the above one is also a buggy as my controller is unable to support
12-bit bus width.?
I've been using the latest u-boot (v2013.01) on ML507 with a custom SDHCI IP. No problems detected with this patch.
The output of both patched and unpatched u-boot seems to be correct. Except for the Data CRC Error (bit 21) in the patched version.
Several things to check:
1) Verify the controller settings on both patched and unpatched u-boot. The printf()s are just prints some IPs (like the one I'm using) don't allow changing the register value on some conditions (ie during CMD_INHIBIT and/or DAT_INHIBIT). This would make the printf()s look correct but the actual register value is incorrect.
2) Try lowering your SDCLK (ie 25Mhz High-speed mode).
3) Try disabling High-speed mode (which limits you to 25MHz Legacy mode).
All the best, Rommel