Re: [PATCH] xilinx: Sync DTs with Linux kernel

st 10. 3. 2021 v 14:11 odesílatel Michal Simek michal.simek@xilinx.com napsal:

There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel:

• ARM: zynq: Fix leds subnode name for zc702/zybo-z7
• arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
• arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
• arm64: dts: zynqmp: Wire up the DisplayPort subsystem
• arm64: dts: zynqmp: Add DisplayPort subsystem
• arm64: dts: zynqmp: Add DPDMA node
• arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
• arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
• arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
• arm64: dts: zynqmp-zcu100-revC: correct interrupt flags
• arm64: dts: xilinx: align GPIO hog names with dtschema
• arm64: zynqmp: Add Xilinx AES node
• dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA

but also some other changes have been done.

• Using only one compatible string for adxl345 on zturn
• Remove Xilinx internal DP bindings
• Remove USB3.0 serdes configurations
• Remove SATA serdes configuration for zc1232
• Resort nvmem_firmware
• Update nand compatible string
• Aling power-domains property for sd0/1

Signed-off-by: Michal Simek michal.simek@xilinx.com

arch/arm/dts/zynq-zc702.dts | 2 +- arch/arm/dts/zynq-zturn-common.dtsi | 2 +- arch/arm/dts/zynq-zybo-z7.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 3 - arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 - arch/arm/dts/zynqmp-zc1232-revA.dts | 2 - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 19 +-- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 48 ++++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 106 ++++++++++---- arch/arm/dts/zynqmp-zcu104-revA.dts | 44 +++++- arch/arm/dts/zynqmp-zcu104-revC.dts | 44 +++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 96 ++++++++++-- arch/arm/dts/zynqmp-zcu111-revA.dts | 78 ++++++++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 58 ++++++-- arch/arm/dts/zynqmp-zcu216-revA.dts | 58 ++++++-- arch/arm/dts/zynqmp.dtsi | 154 +++++--------------- include/dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 ++ 19 files changed, 498 insertions(+), 255 deletions(-) create mode 100644 include/dt-bindings/dma/xlnx-zynqmp-dpdma.h

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index b043d341d680..e45eba3d90b3 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -51,7 +51,7 @@ leds { compatible = "gpio-leds";

•           ds23 {
  

•           led-ds23 {
                    label = "ds23";
                    gpios = <&gpio0 10 0>;
                    linux,default-trigger = "heartbeat";
  

diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi index 1d7af02893dc..486b6fa2e1b8 100644 --- a/arch/arm/dts/zynq-zturn-common.dtsi +++ b/arch/arm/dts/zynq-zturn-common.dtsi @@ -112,7 +112,7 @@ };

    accelerometer@53 {

•           compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
  

•           compatible = "adi,adxl345";
            reg = <0x53>;
            interrupt-parent = <&intc>;
            interrupts = <0x0 0x1e 0x4>;
  

diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts index 3f8a3bfa0ff7..116958ec97aa 100644 --- a/arch/arm/dts/zynq-zybo-z7.dts +++ b/arch/arm/dts/zynq-zybo-z7.dts @@ -31,7 +31,7 @@ gpio-leds { compatible = "gpio-leds";

•           ld4 {
  

•           led-ld4 {
                    label = "zynq-zybo-z7:green:ld4";
                    gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
            };
  

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index b02ef22abd20..987792e5c511 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -284,18 +284,16 @@ clocks = <&zynqmp_clk AMS_REF>; };

-&zynqmp_dpsub {

•   clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
  

+&zynqmp_pcap {

•   clocks = <&zynqmp_clk PCAP>;
  

};

-&xlnx_dpdma { +&zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; };

-&zynqmp_dp_snd_codec0 {

•   clocks = <&zynqmp_clk DP_AUDIO_REF>;
  

-};

-&zynqmp_pcap {

•   clocks = <&zynqmp_clk PCAP>;
  

+&zynqmp_dpsub {

•   clocks = <&zynqmp_clk TOPSW_LSBUS>,
  

•            <&zynqmp_clk DP_AUDIO_REF>,
  

•            <&zynqmp_clk DP_VIDEO_REF>;
  

}; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 9468dc574fd8..f94b797d1a24 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -88,9 +88,6 @@ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ }; -/* phy-names = "...";

•   phys = <&lane0 PHY_TYPE_SGMII ... >
  

•   Note: lane0 sgmii/lane1 usb3 */
  

};

&gpio { diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 66ea02e5be7f..19e1ebdb1d6a 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -118,9 +118,6 @@ reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ }; -/* phy-names = "...";

•   phys = <&lane0 PHY_TYPE_SGMII ... >
  

•   Note: lane0 sgmii/lane1 usb3 */
  

};

&gpio { diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index afb3e96520b8..ef7cf0a36b21 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -78,8 +78,6 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;

•   phy-names = "sata-phy";
  

•   phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
  

};

&uart0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index e2428ec974a3..b8c5efb6a914 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -175,26 +175,11 @@ dr_mode = "host"; };

-&zynqmp_dpsub {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_pcm0 {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_pcm1 { +&zynqmp_dpdma { status = "okay"; };

-&zynqmp_dp_snd_card0 {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_codec0 { +&zynqmp_dpsub { status = "okay"; };

-&xlnx_dpdma {

•   status = "okay";
  

-}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 9b38b8b919e2..aadda179c323 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -119,7 +119,7 @@ status = "okay"; };

-&xlnx_dpdma { +&zynqmp_dpdma { status = "okay"; };

diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index d6c914c917f5..bbcc69c79673 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -69,27 +69,27 @@

    leds {
            compatible = "gpio-leds";

•           ds2 {
  

•           led-ds2 {
                    label = "ds2";
                    gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
                    linux,default-trigger = "heartbeat";
            };
  
  

•           ds3 {
  

•           led-ds3 {
                    label = "ds3";
                    gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
                    linux,default-trigger = "phy0tx"; /* WLAN tx */
                    default-state = "off";
            };
  
  

•           ds4 {
  

•           led-ds4 {
                    label = "ds4";
                    gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
                    linux,default-trigger = "phy0rx"; /* WLAN rx */
                    default-state = "off";
            };
  
  

•           ds5 {
  

•           led-ds5 {
                    label = "ds5";
                    gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
                    linux,default-trigger = "bluetooth-power";
  

@@ -130,6 +130,18 @@ compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; };

•   si5335a_0: clk26 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <26000000>;
  

•   };
  

•   si5335a_1: clk27 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <27000000>;
  

•   };
  

};

&dcc { @@ -212,7 +224,7 @@ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>;

•                           interrupts = <77 GPIO_ACTIVE_LOW>;
  

•                           interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
                            #gpio-cells = <2>;
                            gpio-controller;
                    };
  

@@ -250,6 +262,13 @@ }; };

+&psgtr {

•   status = "okay";
  

•   /* usb3, dps */
  

•   clocks = <&si5335a_0>, <&si5335a_1>;
  

•   clock-names = "ref0", "ref1";
  

+};

&rtc { status = "okay"; }; @@ -281,10 +300,6 @@ }; };

-&serdes {

•   status = "okay";
  

-};

&spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; @@ -318,8 +333,6 @@ &dwc3_0 { status = "okay"; dr_mode = "peripheral";

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
    maximum-speed = "super-speed";
  

};

@@ -331,8 +344,6 @@ &dwc3_1 { status = "okay"; dr_mode = "host";

•   phy-names = "usb3-phy";
  

•   phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;
    maximum-speed = "super-speed";
  

};

@@ -347,3 +358,14 @@ &ams_ps { status = "okay"; };

+&zynqmp_dpdma {

•   status = "okay";
  

+};

+&zynqmp_dpsub {

•   status = "okay";
  

•   phy-names = "dp-phy0", "dp-phy1";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
  

•          <&psgtr 0 PHY_TYPE_DP 1 1>;
  

+}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ed036e68f5e3..9323b8d64d56 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -137,6 +137,19 @@ compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; };

•   /* 48MHz reference crystal */
  

•   ref48: ref48M {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <48000000>;
  

•   };
  

•   refhdmi: refhdmi {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <114285000>;
  

•   };
  

};

&can1 { @@ -213,25 +226,25 @@ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", "";

•           gtr-sel0 {
  

•           gtr-sel0-hog {
                    gpio-hog;
                    gpios = <0 0>;
                    output-low; /* PCIE = 0, DP = 1 */
                    line-name = "sel0";
            };
  

•           gtr-sel1 {
  

•           gtr-sel1-hog {
                    gpio-hog;
                    gpios = <1 0>;
                    output-high; /* PCIE = 0, DP = 1 */
                    line-name = "sel1";
            };
  

•           gtr-sel2 {
  

•           gtr-sel2-hog {
                    gpio-hog;
                    gpios = <2 0>;
                    output-high; /* PCIE = 0, USB0 = 1 */
                    line-name = "sel2";
            };
  

•           gtr-sel3 {
  

•           gtr-sel3-hog {
                    gpio-hog;
                    gpios = <3 0>;
                    output-high; /* PCIE = 0, SATA = 1 */
  

@@ -494,8 +507,54 @@ si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>;

•                           #clock-cells = <2>;
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           clocks = <&ref48>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5341";
  

•                           si5341_0: out@0 {
  

•                                   /* refclk0 for PS-GT, used for DP */
  

•                                   reg = <0>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_2: out@2 {
  

•                                   /* refclk2 for PS-GT, used for USB3 */
  

•                                   reg = <2>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_3: out@3 {
  

•                                   /* refclk3 for PS-GT, used for SATA */
  

•                                   reg = <3>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_4: out@4 {
  

•                                   /* refclk4 for PS-GT, used for PCIE slot */
  

•                                   reg = <4>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_5: out@5 {
  

•                                   /* refclk5 for PS-GT, used for PCIE */
  

•                                   reg = <5>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_6: out@6 {
  

•                                   /* refclk6 PL CLK125 */
  

•                                   reg = <6>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_7: out@7 {
  

•                                   /* refclk7 PL CLK74 */
  

•                                   reg = <7>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_9: out@9 {
  

•                                   /* refclk9 used for PS_REF_CLK 33.3 MHz */
  

•                                   reg = <9>;
  

•                                   always-on;
  

•                           };
                    };
  

•           };
            i2c@2 {
                    #address-cells = <1>;
  

@@ -603,6 +662,13 @@ status = "okay"; };

+&psgtr {

•   status = "okay";
  

•   /* pcie, sata, usb3, dp */
  

•   clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
  

•   clock-names = "ref0", "ref1", "ref2", "ref3";
  

+};

&qspi { status = "okay"; is-dual = <1>; @@ -649,7 +715,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy";

•   phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
  

};

/* SD1 with level shifter */ @@ -663,10 +729,6 @@ xlnx,mio-bank = <1>; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -684,8 +746,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
    maximum-speed = "super-speed";
  

};

@@ -705,26 +765,12 @@ status = "okay"; };

-&zynqmp_dpsub { +&zynqmp_dpdma { status = "okay"; };

-&zynqmp_dp_snd_codec0 {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_pcm0 {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_pcm1 {

•   status = "okay";
  

-};

-&zynqmp_dp_snd_card0 {

•   status = "okay";
  

-};

-&xlnx_dpdma { +&zynqmp_dpsub { status = "okay";

•   phy-names = "dp-phy0";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
  

}; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index cb8ffdff9771..a95bd4922a62 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -40,6 +40,24 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; };

•   clock_8t49n287_5: clk125 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <125000000>;
  

•   };
  

•   clock_8t49n287_2: clk26 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <26000000>;
  

•   };
  

•   clock_8t49n287_3: clk27 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <27000000>;
  

•   };
  

};

&can1 { @@ -226,6 +244,13 @@ }; };

+&psgtr {

•   status = "okay";
  

•   /* nc, sata, usb3, dp */
  

•   clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
  

•   clock-names = "ref1", "ref2", "ref3";
  

+};

&rtc { status = "okay"; }; @@ -242,7 +267,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy";

•   phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
  

};

/* SD1 with level shifter */ @@ -253,10 +278,6 @@ disable-wp; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -274,8 +295,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
    maximum-speed = "super-speed";
  

};

@@ -294,3 +313,14 @@ &ams_pl { status = "okay"; };

+&zynqmp_dpdma {

•   status = "okay";
  

+};

+&zynqmp_dpsub {

•   status = "okay";
  

•   phy-names = "dp-phy0", "dp-phy1";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
  

•          <&psgtr 0 PHY_TYPE_DP 1 3>;
  

+}; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index e203280f0eca..8f30a2883e27 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -46,6 +46,24 @@ compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; };

•   clock_8t49n287_5: clk125 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <125000000>;
  

•   };
  

•   clock_8t49n287_2: clk26 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <26000000>;
  

•   };
  

•   clock_8t49n287_3: clk27 {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <27000000>;
  

•   };
  

};

&can1 { @@ -243,6 +261,13 @@ status = "okay"; };

+&psgtr {

•   status = "okay";
  

•   /* nc, sata, usb3, dp */
  

•   clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
  

•   clock-names = "ref1", "ref2", "ref3";
  

+};

&sata { status = "okay"; /* SATA OOB timing settings */ @@ -255,7 +280,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy";

•   phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
  

};

/* SD1 with level shifter */ @@ -266,10 +291,6 @@ disable-wp; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -287,8 +308,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
    maximum-speed = "super-speed";
  

};

@@ -307,3 +326,14 @@ &ams_pl { status = "okay"; };

+&zynqmp_dpdma {

•   status = "okay";
  

+};

+&zynqmp_dpsub {

•   status = "okay";
  

•   phy-names = "dp-phy0", "dp-phy1";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
  

•          <&psgtr 0 PHY_TYPE_DP 1 3>;
  

+}; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 1dff845ceeb6..971f76f1cabe 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -137,6 +137,19 @@ compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; };

•   /* 48MHz reference crystal */
  

•   ref48: ref48M {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <48000000>;
  

•   };
  

•   refhdmi: refhdmi {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <114285000>;
  

•   };
  

};

&can1 { @@ -147,6 +160,18 @@ status = "okay"; };

+&zynqmp_dpdma {

•   status = "okay";
  

+};

+&zynqmp_dpsub {

•   status = "okay";
  

•   phy-names = "dp-phy0", "dp-phy1";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
  

•          <&psgtr 0 PHY_TYPE_DP 1 3>;
  

+};

+/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -490,8 +515,45 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */

•                           compatible = "si5341";
  

•                           compatible = "silabs,si5341";
                            reg = <0x36>;
  

•                           #clock-cells = <2>;
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           clocks = <&ref48>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5341";
  

•                           si5341_0: out@0 {
  

•                                   /* refclk0 for PS-GT, used for DP */
  

•                                   reg = <0>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_2: out@2 {
  

•                                   /* refclk2 for PS-GT, used for USB3 */
  

•                                   reg = <2>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_3: out@3 {
  

•                                   /* refclk3 for PS-GT, used for SATA */
  

•                                   reg = <3>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_6: out@6 {
  

•                                   /* refclk6 PL CLK125 */
  

•                                   reg = <6>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_7: out@7 {
  

•                                   /* refclk7 PL CLK74 */
  

•                                   reg = <7>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_9: out@9 {
  

•                                   /* refclk9 used for PS_REF_CLK 33.3 MHz */
  

•                                   reg = <9>;
  

•                                   always-on;
  

•                           };
                    };
  
            };
  

@@ -528,8 +590,23 @@ #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */

•                           compatible = "silabs,si5328";
                            reg = <0x69>;
  

•                           /*
  

•                            * Chip has interrupt present connected to PL
  

•                            * interrupt-parent = <&>;
  

•                            * interrupts = <>;
  

•                            */
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           #clock-cells = <1>;
  

•                           clocks = <&refhdmi>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5328";
  

•                           si5328_clk: clk0@0 {
  

•                                   reg = <0>;
  

•                                   clock-frequency = <27000000>;
  

•                           };
                    };
            };
            i2c@5 {
  

@@ -601,6 +678,13 @@ }; };

+&psgtr {

•   status = "okay";
  

•   /* nc, sata, usb3, dp */
  

•   clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
  

•   clock-names = "ref1", "ref2", "ref3";
  

+};

&qspi { status = "okay"; is-dual = <1>; @@ -647,7 +731,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy";

•   phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
  

};

/* SD1 with level shifter */ @@ -660,10 +744,6 @@ xlnx,mio-bank = <1>; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -681,8 +761,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  

};

&watchdog0 { diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 82e6c8d3cdfd..9e47008542ae 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -121,6 +121,13 @@ compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; };

•   /* 48MHz reference crystal */
  

•   ref48: ref48M {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <48000000>;
  

•   };
  

};

&dcc { @@ -386,10 +393,46 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */

•                           compatible = "si5341";
  

•                           compatible = "silabs,si5341";
                            reg = <0x36>;
  

•                           #clock-cells = <2>;
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           clocks = <&ref48>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5341";
  

•                           si5341_0: out@0 {
  

•                                   /* refclk0 for PS-GT, used for DP */
  

•                                   reg = <0>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_2: out@2 {
  

•                                   /* refclk2 for PS-GT, used for USB3 */
  

•                                   reg = <2>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_3: out@3 {
  

•                                   /* refclk3 for PS-GT, used for SATA */
  

•                                   reg = <3>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_5: out@5 {
  

•                                   /* refclk5 PL CLK100 */
  

•                                   reg = <5>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_6: out@6 {
  

•                                   /* refclk6 PL CLK125 */
  

•                                   reg = <6>;
  

•                                   always-on;
  

•                           };
  

•                           si5341_9: out@9 {
  

•                                   /* refclk9 used for PS_REF_CLK 33.3 MHz */
  

•                                   reg = <9>;
  

•                                   always-on;
  

•                           };
                    };
  

•           };
            i2c@2 {
                    #address-cells = <1>;
  

@@ -423,8 +466,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>;

•                   si5328: clock-generator@69 { /* SI5328 - u48 */
  

•                           compatible = "silabs,si5328";
  

•                   si5382: clock-generator@69 { /* SI5382 - u48 */
  

•                           compatible = "silabs,si5382";
                            reg = <0x69>;
                    };
            };
  

@@ -511,6 +554,13 @@ }; };

+&psgtr {

•   status = "okay";
  

•   /* nc, sata, usb3, dp */
  

•   clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
  

•   clock-names = "ref1", "ref2", "ref3";
  

+};

&qspi { status = "okay"; is-dual = <1>; @@ -557,7 +607,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy";

•   phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
  

};

/* SD1 with level shifter */ @@ -571,10 +621,6 @@ xlnx,mio-bank = <1>; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -582,12 +628,16 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay";

•   dr_mode = "host";
  

};

-&dwc3_0 { +&zynqmp_dpdma { status = "okay";

•   dr_mode = "host";
  

•   snps,usb3_lpm_capable;
  

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  

+};

+&zynqmp_dpsub {

•   status = "okay";
  

•   phy-names = "dp-phy0", "dp-phy1";
  

•   phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
  

•          <&psgtr 0 PHY_TYPE_DP 1 1>;
  

}; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 268e368b7657..0e114cdacb1a 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -120,6 +120,13 @@ compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; };

•   /* 48MHz reference crystal */
  

•   ref48: ref48M {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <48000000>;
  

•   };
  

};

&dcc { @@ -404,10 +411,41 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */

•                           compatible = "si5341";
  

•                           compatible = "silabs,si5341";
                            reg = <0x36>;
  

•                           #clock-cells = <2>;
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           clocks = <&ref48>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5341";
  

•                           si5341_2: out@2 {
  

•                                   /* refclk2 for PS-GT, used for USB3 */
  

•                                   reg = <2>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_3: out@3 {
  

•                                   /* refclk3 for PS-GT, used for SATA */
  

•                                   reg = <3>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_5: out@5 {
  

•                                   /* refclk5 PL CLK100 */
  

•                                   reg = <5>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_6: out@6 {
  

•                                   /* refclk6 PL CLK125 */
  

•                                   reg = <6>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_9: out@9 {
  

•                                   /* refclk9 used for PS_REF_CLK 33.3 MHz */
  

•                                   reg = <9>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
                    };
  

•           };
            i2c_si570_user_c0: i2c@2 {
                    #address-cells = <1>;
  

@@ -541,6 +579,13 @@ }; };

+&psgtr {

•   status = "okay";
  

•   /* pcie, sata, usb3, dp */
  

•   clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
  

•   clock-names = "ref0", "ref1", "ref2", "ref3";
  

+};

&rtc { status = "okay"; }; @@ -556,8 +601,7 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;

•   phy-names = "sata-phy";
  

•   phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
  

};

/* SD1 with level shifter */ @@ -571,10 +615,6 @@ xlnx,mio-bank = <1>; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -588,6 +628,4 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  

}; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 847e689c155f..2302b07c4825 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -120,6 +120,20 @@ compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; };

•   /* 48MHz reference crystal */
  

•   ref48: ref48M {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <48000000>;
  

•   };
  

+};

+&psgtr {

•   status = "okay";
  

•   /* pcie, sata, usb3, dp */
  

•   clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
  

•   clock-names = "ref0", "ref1", "ref2", "ref3";
  

};

&dcc { @@ -408,10 +422,41 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */

•                           compatible = "si5341";
  

•                           compatible = "silabs,si5341";
                            reg = <0x36>;
  

•                           #clock-cells = <2>;
  

•                           #address-cells = <1>;
  

•                           #size-cells = <0>;
  

•                           clocks = <&ref48>;
  

•                           clock-names = "xtal";
  

•                           clock-output-names = "si5341";
  

•                           si5341_2: out@2 {
  

•                                   /* refclk2 for PS-GT, used for USB3 */
  

•                                   reg = <2>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_3: out@3 {
  

•                                   /* refclk3 for PS-GT, used for SATA */
  

•                                   reg = <3>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_5: out@5 {
  

•                                   /* refclk5 PL CLK100 */
  

•                                   reg = <5>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_6: out@6 {
  

•                                   /* refclk6 PL CLK125 */
  

•                                   reg = <6>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
  

•                           si5341_9: out@9 {
  

•                                   /* refclk9 used for PS_REF_CLK 33.3 MHz */
  

•                                   reg = <9>;
  

•                                   always-on; /* assigned-clocks does not enable, so do it here */
  

•                           };
                    };
  

•           };
            i2c_si570_user_c0: i2c@2 {
                    #address-cells = <1>;
  

@@ -560,8 +605,7 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;

•   phy-names = "sata-phy";
  

•   phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
  

•   phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
  

};

/* SD1 with level shifter */ @@ -575,10 +619,6 @@ xlnx,mio-bank = <1>; };

-&serdes {

•   status = "okay";
  

-};

&uart0 { status = "okay"; }; @@ -592,6 +632,4 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable;

•   phy-names = "usb3-phy";
  

•   phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  

}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2917a956eb3d..84d9770225aa 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -12,6 +12,7 @@

• the License, or (at your option) any later version.

*/

+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

@@ -160,11 +161,25 @@ mbox-names = "tx", "rx"; };

•                   nvmem_firmware {
  

•                           compatible = "xlnx,zynqmp-nvmem-fw";
  

•                           #address-cells = <1>;
  

•                           #size-cells = <1>;
  

•                           soc_revision: soc_revision@0 {
  

•                                   reg = <0x0 0x4>;
  

•                           };
  

•                   };
  

•                   zynqmp_pcap: pcap {
                            compatible = "xlnx,zynqmp-pcap-fpga";
                            clock-names = "ref_clk";
                    };
  
  

•                   xlnx_aes: zynqmp-aes {
  

•                           compatible = "xlnx,zynqmp-aes";
  

•                   };
  

•                   zynqmp_reset: reset-controller {
                            compatible = "xlnx,zynqmp-reset";
                            #reset-cells = <1>;
  

@@ -198,16 +213,6 @@ ranges; };

•   nvmem_firmware {
  

•           compatible = "xlnx,zynqmp-nvmem-fw";
  

•           #address-cells = <1>;
  

•           #size-cells = <1>;
  

•           soc_revision: soc_revision@0 {
  

•                   reg = <0x0 0x4>;
  

•           };
  

•   };
  

•   amba: axi {
            compatible = "simple-bus";
            u-boot,dm-pre-reloc;
  

@@ -501,8 +506,8 @@ interrupts = <0 112 4>; };

•           nand0: nand@ff100000 {
  

•                   compatible = "arasan,nfc-v3p10";
  

•           nand0: nand-controller@ff100000 {
  

•                   compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
                    status = "disabled";
                    reg = <0x0 0xff100000 0x0 0x1000>;
                    clock-names = "controller", "bus";
  

@@ -667,6 +672,15 @@ power-domains = <&zynqmp_firmware PD_QSPI>; };

•           psgtr: phy@fd400000 {
  

•                   compatible = "xlnx,zynqmp-psgtr-v1.1";
  

•                   status = "disabled";
  

•                   reg = <0x0 0xfd400000 0x0 0x40000>,
  

•                         <0x0 0xfd3d0000 0x0 0x1000>;
  

•                   reg-names = "serdes", "siou";
  

•                   #phy-cells = <4>;
  

•           };
  

•           rtc: rtc@ffa60000 {
                    compatible = "xlnx,zynqmp-rtc";
                    status = "disabled";
  

@@ -677,45 +691,6 @@ calibration = <0x8000>; };

•           serdes: zynqmp_phy@fd400000 {
  

•                   compatible = "xlnx,zynqmp-psgtr";
  

•                   status = "disabled";
  

•                   reg = <0x0 0xfd400000 0x0 0x40000>,
  

•                         <0x0 0xfd3d0000 0x0 0x1000>,
  

•                         <0x0 0xff5e0000 0x0 0x1000>;
  

•                   reg-names = "serdes", "siou", "lpd";
  

•                   nvmem-cells = <&soc_revision>;
  

•                   nvmem-cell-names = "soc_revision";
  

•                   resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_DP>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_GEM0>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_GEM1>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_GEM2>,
  

•                            <&zynqmp_reset ZYNQMP_RESET_GEM3>;
  

•                   reset-names = "sata_rst", "usb0_crst", "usb1_crst",
  

•                                 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
  

•                                 "usb1_apbrst", "dp_rst", "gem0_rst",
  

•                                 "gem1_rst", "gem2_rst", "gem3_rst";
  

•                   lane0: lane0 {
  

•                           #phy-cells = <4>;
  

•                   };
  

•                   lane1: lane1 {
  

•                           #phy-cells = <4>;
  

•                   };
  

•                   lane2: lane2 {
  

•                           #phy-cells = <4>;
  

•                   };
  

•                   lane3: lane3 {
  

•                           #phy-cells = <4>;
  

•                   };
  

•           };
  

•           sata: ahci@fd0c0000 {
                    compatible = "ceva,ahci-1v84";
                    status = "disabled";
  

@@ -740,11 +715,11 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>;

•                   power-domains = <&zynqmp_firmware PD_SD_0>;
                    nvmem-cells = <&soc_revision>;
                    nvmem-cell-names = "soc_revision";
                    #clock-cells = <1>;
                    clock-output-names = "clk_out_sd0", "clk_in_sd0";
  

•                   power-domains = <&zynqmp_firmware PD_SD_0>;
            };
  
            sdhci1: mmc@ff170000 {
  

@@ -758,11 +733,11 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>;

•                   power-domains = <&zynqmp_firmware PD_SD_1>;
                    nvmem-cells = <&soc_revision>;
                    nvmem-cell-names = "soc_revision";
                    #clock-cells = <1>;
                    clock-output-names = "clk_out_sd1", "clk_in_sd1";
  

•                   power-domains = <&zynqmp_firmware PD_SD_1>;
            };
  
            smmu: iommu@fd800000 {
  

@@ -962,37 +937,18 @@ }; };

•           xlnx_dpdma: dma@fd4c0000 {
  

•                   compatible = "xlnx,dpdma";
  

•           zynqmp_dpdma: dma-controller@fd4c0000 {
  

•                   compatible = "xlnx,zynqmp-dpdma";
                    status = "disabled";
                    reg = <0x0 0xfd4c0000 0x0 0x1000>;
                    interrupts = <0 122 4>;
                    interrupt-parent = <&gic>;
                    clock-names = "axi_clk";
                    power-domains = <&zynqmp_firmware PD_DP>;
  

•                   dma-channels = <6>;
                    #dma-cells = <1>;
  

•                   dma-video0channel {
  

•                           compatible = "xlnx,video0";
  

•                   };
  

•                   dma-video1channel {
  

•                           compatible = "xlnx,video1";
  

•                   };
  

•                   dma-video2channel {
  

•                           compatible = "xlnx,video2";
  

•                   };
  

•                   dma-graphicschannel {
  

•                           compatible = "xlnx,graphics";
  

•                   };
  

•                   dma-audio0channel {
  

•                           compatible = "xlnx,audio0";
  

•                   };
  

•                   dma-audio1channel {
  

•                           compatible = "xlnx,audio1";
  

•                   };
            };
  
  

•           zynqmp_dpsub: zynqmp-display@fd4a0000 {
  

•           zynqmp_dpsub: display@fd4a0000 {
                    compatible = "xlnx,zynqmp-dpsub-1.7";
                    status = "disabled";
                    reg = <0x0 0xfd4a0000 0x0 0x1000>,
  

@@ -1002,51 +958,15 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>;

•                   clock-names = "dp_apb_clk", "dp_aud_clk",
                                  "dp_vtc_pixel_clk_in";
  

•                   power-domains = <&zynqmp_firmware PD_DP>;
  

•                   vid-layer {
  

•                           dma-names = "vid0", "vid1", "vid2";
  

•                           dmas = <&xlnx_dpdma 0>,
  

•                                  <&xlnx_dpdma 1>,
  

•                                  <&xlnx_dpdma 2>;
  

•                   };
  

•                   gfx-layer {
  

•                           dma-names = "gfx0";
  

•                           dmas = <&xlnx_dpdma 3>;
  

•                   };
  

•                   /* dummy node to indicate there's no child i2c device */
  

•                   i2c-bus {
  

•                   };
  

•                   zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
  

•                           compatible = "xlnx,dp-snd-codec";
  

•                           clock-names = "aud_clk";
  

•                   };
  

•                   zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
  

•                           compatible = "xlnx,dp-snd-pcm";
  

•                           dmas = <&xlnx_dpdma 4>;
  

•                           dma-names = "tx";
  

•                   };
  

•                   zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
  

•                           compatible = "xlnx,dp-snd-pcm";
  

•                           dmas = <&xlnx_dpdma 5>;
  

•                           dma-names = "tx";
  

•                   };
  

•                   zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
  

•                           compatible = "xlnx,dp-snd-card";
  

•                           xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
  

•                                             <&zynqmp_dp_snd_pcm1>;
  

•                           xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
  

•                   };
  

•                   resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
  

•                   dma-names = "vid0", "vid1", "vid2", "gfx0";
  

•                   dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
  

•                          <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
  

•                          <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
  

•                          <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
            };
    };
  

}; diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h new file mode 100644 index 000000000000..3719cda5679d --- /dev/null +++ b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/*

• • Copyright 2019 Laurent Pinchart laurent.pinchart@ideasonboard.com
• */

+#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__

+#define ZYNQMP_DPDMA_VIDEO0 0 +#define ZYNQMP_DPDMA_VIDEO1 1 +#define ZYNQMP_DPDMA_VIDEO2 2 +#define ZYNQMP_DPDMA_GRAPHICS 3 +#define ZYNQMP_DPDMA_AUDIO0 4 +#define ZYNQMP_DPDMA_AUDIO1 5

+#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */

2.30.1

Applied. M