From: Harini Katakam harini.katakam@amd.com
TI phy requires a reset before PHY address detection to make sure correct strapping via MIO is detected. Facilitate the same using ethernet-phy-id compatible string. GPIO reset entry will be added in a separate commit. This support is present in RevA but needs to be extended to RevB/1.0/1.1 versions which are built on top.
Fixes: 13622c7a9dfa ("arm64: zynqmp: Describe TI phy as ethernet-phy-id") Signed-off-by: Harini Katakam harini.katakam@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-zcu102-revB.dts | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 2422558b7484..b2f0b1133175 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -16,16 +16,20 @@
&gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; };
/* Fix collision with u61 */