27 Dec
2024
27 Dec
'24
7:23 p.m.
On Fri, Dec 27, 2024 at 10:19:34AM +0530, Venkatesh Yadav Abbarapu wrote:
Update the spi_nor_read() function based on the config SPI_FLASH_BAR and update the length and bank calculation by spliting the memory of 16MB size banks only when the address width is 3byte. Fix the read issue for 4byte address width by passing the entire length to the read function. Also update the size when the configuration is stacked.
Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
I don't think you've run this through CI? https://source.denx.de/u-boot/u-boot/-/jobs/984698#L289 and similar on all sandbox targets, and Azure shows it too.
--
Tom