MAIN_PLL0 has a flag set in DM (Device Manager) that removes its capability to re-initialise clock frequencies. A72 CPU clock (GTC) and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs re-initialization to default frequency to be able to get 250MHz with its divider, GTC can not get its required 200MHz with its dividers. Thus move GTC clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. This was already done on CPTS node in kernel which was similarly affected (linked).
Link: https://lore.kernel.org/all/20230605110443.84568-1-n-francis@ti.com/ Signed-off-by: Neha Malcom Francis n-francis@ti.com --- Boot logs: https://gist.github.com/nehamalcom/70676857dc3816a415af9861c38c76eb
arch/arm/dts/k3-j721s2-r5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index eb0df42583a..40272abfc7c 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -22,7 +22,7 @@ resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-parents = <&k3_clks 61 3>; assigned-clock-rates = <200000000>, <2000000000>; ti,sci = <&sms>; ti,sci-proc-id = <32>;