In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init.
Signed-off-by: Marek Behun marek.behun@nic.cz Reviewed-by: Stefan Roese sr@denx.de --- drivers/phy/marvell/comphy_a3700.c | 9 ++++++++- drivers/phy/marvell/comphy_a3700.h | 1 - 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 8b44732e52..7f5371afe9 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -698,13 +698,15 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) { int ret; + u32 saved_selector;
debug_enter();
/* * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 */ - reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); + saved_selector = readl(COMPHY_SEL_ADDR); + reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
/* * 2. Reset PHY by setting PHY input port PIN_RESET=1. @@ -875,6 +877,11 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) if (!ret) printf("Failed to init RX of SGMII PHY %d\n", lane);
+ /* + * Restore saved selector. + */ + reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); + debug_exit();
return ret; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 2468468162..6d737967ab 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -23,7 +23,6 @@ * COMPHY SB definitions */ #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC) -#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28) #define rb_pin_pu_iveref BIT(1)