Signed-off-by: Joonyoung Shim jy0922.shim@samsung.com Signed-off-by: Lukasz Majewski l.majewski@samsung.com [The code has been rebased on v2 dwc3 support provided by Kishon Vijay Abraham I] --- drivers/usb/dwc3/core.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++- drivers/usb/dwc3/core.h | 1 + include/dwc3-uboot.h | 2 ++ 3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d690870..fc3b0d9 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -14,7 +14,12 @@ * SPDX-License-Identifier: GPL-2.0 */
+#include "linux-compat.h" + #include <common.h> +#include <asm/arch/power.h> +#include <asm/arch/xhci-exynos.h> +#include <asm/cache.h> #include <malloc.h> #include <dwc3-uboot.h> #include <asm/dma-mapping.h> @@ -42,6 +47,71 @@ static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) dwc3_writel(dwc->regs, DWC3_GCTL, reg); }
+static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) +{ + u32 reg; + + /* Reset USB 3.0 PHY */ + writel(0x0, &phy->phy_reg0); + + clrbits_le32(&phy->phy_param0, + /* Select PHY CLK source */ + PHYPARAM0_REF_USE_PAD | + /* Set Loss-of-Signal Detector sensitivity */ + PHYPARAM0_REF_LOSLEVEL_MASK); + setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); + + + writel(0x0, &phy->phy_resume); + + /* + * Setting the Frame length Adj value[6:1] to default 0x20 + * See xHCI 1.0 spec, 5.2.4 + */ + setbits_le32(&phy->link_system, + LINKSYSTEM_XHCI_VERSION_CONTROL | + LINKSYSTEM_FLADJ(0x20)); + + /* Set Tx De-Emphasis level */ + clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); + setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); + + setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); + + /* PHYTEST POWERDOWN Control */ + clrbits_le32(&phy->phy_test, + PHYTEST_POWERDOWN_SSP | + PHYTEST_POWERDOWN_HSP); + + /* UTMI Power Control */ + writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); + + /* Use core clock from main PLL */ + reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | + /* Default 24Mhz crystal clock */ + PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | + PHYCLKRST_SSC_REFCLKSEL(0) | + /* Force PortReset of PHY */ + PHYCLKRST_PORTRESET | + /* Digital power supply in normal operating mode */ + PHYCLKRST_RETENABLEN | + /* Enable ref clock for SS function */ + PHYCLKRST_REF_SSP_EN | + /* Enable spread spectrum */ + PHYCLKRST_SSC_EN | + /* Power down HS Bias and PLL blocks in suspend mode */ + PHYCLKRST_COMMONONN; + + writel(reg, &phy->phy_clk_rst); + + /* giving time to Phy clock to settle before resetting */ + udelay(10); + + reg &= ~PHYCLKRST_PORTRESET; + writel(reg, &phy->phy_clk_rst); +} + /** * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure @@ -66,6 +136,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100); + exynos5_usb3_phy_init((struct exynos_usb3_phy *)dwc->phy_regs);
/* Clear USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); @@ -599,6 +670,7 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
#define DWC3_ALIGN_MASK (16 - 1)
+void set_usbdrd_phy_ctrl(unsigned int enable); /** * dwc3_uboot_init - dwc3 core uboot initialization code * @dwc3_dev: struct dwc3_device containing initialization data @@ -629,7 +701,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); dwc->mem = mem;
- dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START); + dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START); + dwc->phy_regs = (int *)(dwc3_dev->phy_base);
/* default to highest possible threshold */ lpm_nyet_threshold = 0xff; @@ -697,6 +770,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) dwc->dr_mode = USB_DR_MODE_OTG;
+ set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); + ret = dwc3_core_init(dwc); if (ret) { dev_err(dev, "failed to initialize core\n"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 45e431b..304e0c1 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -727,6 +727,7 @@ struct dwc3 {
void __iomem *regs; size_t regs_size; + void __iomem *phy_regs;
enum usb_dr_mode dr_mode;
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 09ff8a7..4c363cb 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -14,6 +14,8 @@
struct dwc3_device { int base; + int phy_base; + unsigned needs_fifo_resize:1; enum usb_dr_mode dr_mode; u32 maximum_speed; unsigned tx_fifo_resize:1;