Hello Fabio and everybody, just a quick update on this old email thread.
On Thu, Dec 02, 2021 at 05:14:28PM +0100, Francesco Dolcini wrote:
In my tests adding 1ms delay after each MMDC register write seems to have a positive effect and this is going into the direction that using `mx6_dram_cfg()` is the way to go.
On Sat, Dec 04, 2021 at 11:29:23AM -0300, Fabio Estevam wrote:
Does it work well if you convert it to the mx6_dram_cfg() scheme?
I did test converting to mx6_dram_cfg() in a couple of problematic samples, and the results are the same as with the "raw" register writes.
If I enable the debug prints everything works fine, exactly as the previous "raw" memory configuration after adding some mdelay(1) in-between each register write.
I'm inclined to exclude any issue on the memory calibration and on the memory timing at the moment (I did triple check those and they should not be affected by any delay on the memory controller register writes).
There should be some kind of requirement on the memory configuration procedure, I wonder if there is some constraints in writing the DDR3 mode registers (there are tMRD and tMOD, for instance ...).
Any advise appreciated!
Thanks Francesco