Le 03/12/2010 16:33, Wolfgang Denk a écrit :
What is the reason that special handling is needed when dcache is enabled? If a driver doesn't use any DMA there should be no need as the dcache is only enabled for the RAM and not for any memory mapped IO if I understand the code in arch/arm/lib/cache-cp15.c right.
On ARM, device write accesses are typically just store instructions (in C: assignments to a volatile pointer). With caches on, these accesses will be - guess what? cached, i. e. they are NOT written to the device, at least not immediately. And if you repeatedly read a register (like when polling for some status bit to change) these accesses will be cached, too.
In addition to making sure that register reads/write are not bitten by caching, note that some controllers have DMA capabilities which require proper cache handling for DMA memory buffers -- typically flushing them from cache before a DMA to the device, and invalidating their cache entries after a DMA from the device.
Best regards,
Wolfgang Denk
Amicalement,