Re: [U-Boot] Cache alignment warnings on Tegra (ARM)

15 Sep 2012


      On Sat, Sep 15, 2012 at 10:01:47PM +0200, Thierry Reding wrote:
...
I think I traced this to the copying of CSD a while back. The problem is
that the transferred buffer is 8 bytes, so there's no way to make it
aligned properly. Unfortunately the entailing discussion did not yield a
solution at the time.
For reference, below is a link[0] to the patch I proposed at the time
but it was obviously wrong. And it wasn't CSD but rather SCR. The reason
why allocating a larger buffer is not enough is that the MMC core
requests that only 8 bytes be transferred, which is the value that
eventually ends up being passed to the cache invalidation routine.
Thierry
[0]: http://lists.denx.de/pipermail/u-boot/2012-April/123080.html