17 May
2007
17 May
'07
5:35 p.m.
On Wed, 2007-05-16 at 18:11, Timur Tabi wrote:
Can you give me some details as to how this works? I'm trying to figure out if this approach is meaningful for boards based on Freescale 8xxx CPUs. I'm guessing it's not, and that the code I see in the board header files is some left-over legacy from a completely different CPU that no one ever bothered to think about.
Timur,
There are test-bed environments, for example, that are capable of setting up some LAWs, configuring DDR, and injecting a new test image into RAM via a JTAG or scan device. From there it is an obvious "boot from RAM" situation useful for rapid turn testing.
jdl