On Thu, Jan 26, 2012 at 5:21 PM, Tom Rini tom.rini@gmail.com wrote:
On Thu, Jan 26, 2012 at 12:35 PM, wilsonjonathan piercing_male@hotmail.com wrote:
On Thu, 2012-01-26 at 12:28 -0700, Tom Rini wrote:
On Thu, Jan 26, 2012 at 12:14 PM, wilsonjonathan piercing_male@hotmail.com wrote:
On Thu, 2012-01-26 at 10:08 -0700, Tom Rini wrote:
On Wed, Jan 25, 2012 at 1:06 PM, wilsonjonathan piercing_male@hotmail.com wrote:
The u-boot loader is showing an incorrect size in the memory, and passing the invalid information to the kernel.
What revision of the board do you have? Is this a 'classic' rev C4? Thanks.
As far as I'm aware yes, standard C4 from digikey.
I've done a little more searching, and found that adding #define DEBUG to /arc/arm/lib/board.c brings up more detailed info.
I will re-confirm with mine then. Previous versions of U-Boot/MLO report how much memory, 512MB?
I don't have an older version to hand, but according to the specs it should be 256MB using a 2Gb MDDR SDRAM and I seem to recall it did display that.
OK, thanks. Does the following fix it for you?
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 5c04b34..1efdbb0 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -161,7 +161,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; *ctrlb = NUMONYX_V_ACTIMB_165; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
Hi Tom,
No change on my c4:
(For reference, i've noticed my older B5,C2 are not affected by this bug..)
U-Boot 2011.12-00004-g79b8c19 (Jan 27 2012 - 08:45:02)
OMAP3530-GP ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 720 mHz OMAP3 Beagle board + LPDDR/NAND I2C: ready DRAM: 1 GiB NAND: 256 MiB MMC: OMAP SD/MMC: 0
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..9aa05d4 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -159,8 +159,8 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { - /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); + /* Beagleboard Rev C4, 256MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(256 << 20); *ctrla = NUMONYX_V_ACTIMA_165; *ctrlb = NUMONYX_V_ACTIMB_165; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
Regards,