On Thursday 26 May 2022 10:52:27 Pali Rohár wrote:
Code for changing boot source is platform generic and can be used by any P1* and P2* compatible RDB board. Not only by boards which use config header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for resetting board and rebooting to other boot source also by other boards in future.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v3:
- Fix copyright header
Priyanka: It is OK now?
Changes in v2:
- Fix commit message
- Move macros to file p1_p2_bootsrc.h
- Rewrite macros even more to be more generic and use them without custom macros in p1_p2_rdb_pc.h
include/configs/p1_p2_bootsrc.h | 59 +++++++++++++++++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 41 +++++------------------ 2 files changed, 68 insertions(+), 32 deletions(-) create mode 100644 include/configs/p1_p2_bootsrc.h
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index 000000000000..13e4fdb4fdf6 --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2010-2011 Freescale Semiconductor, Inc.
- Copyright 2020 NXP
- Copyright 2022 Pali Rohár pali@kernel.org
- */
+#include <linux/stringify.h>
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
+#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif
+#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif
+#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif
+#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif
+#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif
+#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif
+#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f6ecf2a7a8b8..0d655818a924 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -542,31 +542,7 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h"
#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -593,13 +569,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +MAP_NOR_LO_CMD(map_lowernorbank) \ +MAP_NOR_UP_CMD(map_uppernorbank) \ +RST_NOR_CMD(norboot) \ +RST_SPI_CMD(spiboot) \ +RST_SD_CMD(sdboot) \ +RST_NAND_CMD(nandboot) \ +RST_PCIE_CMD(pciboot) \ +""
#define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ -- 2.20.1