[U-Boot] [PATCH ARM 4/4] Change s3c24x0 register struct members to lower case

Changes the names of the s3c24x0 register struct members from upper-case to lower-case.

Signed-off-by: Kevin Morfitt kevin.morfitt@fearnside-systems.co.uk ---

checkpatch.pl reports no errors. MAKEALL ARM9 reports no new warnings or errors.

Note that this is based on the u-boot-master repository. The versions of s3c24x0_nand.c file are different in the u-boot-samsung, u-boot-nand-flash and u-boot-master repositories.

board/mpl/vcma9/vcma9.c | 42 ++-- board/mpl/vcma9/vcma9.h | 20 +- board/samsung/smdk2400/smdk2400.c | 29 +- board/samsung/smdk2410/smdk2410.c | 38 ++- board/sbc2410x/sbc2410x.c | 46 ++-- board/trab/auto_update.c | 1 + board/trab/cmd_trab.c | 36 ++- board/trab/rs485.c | 44 ++- board/trab/trab.c | 71 ++-- board/trab/trab_fkt.c | 159 +++++---- board/trab/tsc2000.c | 38 +- board/trab/tsc2000.h | 112 ++++--- board/trab/vfd.c | 89 +++--- cpu/arm920t/s3c24x0/interrupts.c | 3 +- cpu/arm920t/s3c24x0/speed.c | 8 +- cpu/arm920t/s3c24x0/timer.c | 18 +- cpu/arm920t/s3c24x0/usb.c | 11 +- cpu/arm920t/s3c24x0/usb_ohci.c | 15 +- drivers/i2c/s3c24x0_i2c.c | 102 +++--- drivers/mtd/nand/s3c2410_nand.c | 24 +- drivers/rtc/s3c24x0_rtc.c | 52 ++-- drivers/serial/serial_s3c24x0.c | 26 +- include/asm-arm/arch-s3c24x0/s3c24x0.h | 578 ++++++++++++++++---------------- 23 files changed, 819 insertions(+), 743 deletions(-)

diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 5401664..73cd260 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -30,6 +30,7 @@ #include <asm/arch/s3c24x0_cpu.h> #include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h>

#include "vcma9.h" #include "../common/common_util.h" @@ -78,43 +79,44 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime);

/* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);

/* some delay between MPLL and UPLL */ delay(4000);

/* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon);

/* some delay between MPLL and UPLL */ delay(8000);

/* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x002AAAAA; - gpio->GPBUP = 0x000002BF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x000037F7; - gpio->GPFCON = 0x00000000; - gpio->GPFUP = 0x00000000; - gpio->GPGCON = 0xFFEAFF5A; - gpio->GPGUP = 0x0000F0DC; - gpio->GPHCON = 0x0028AAAA; - gpio->GPHUP = 0x00000656; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup);

/* setup correct IRQ modes for NIC */ /* rising edge mode */ - gpio->EXTINT2 = (gpio->EXTINT2 & ~(7 << 8)) | (4 << 8); + writel((readl(&gpio->extint2) & ~(7 << 8)) | (4 << 8), &gpio->extint2);

/* select USB port 2 to be host or device (fix to host for now) */ - gpio->MISCCR |= 0x08; + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);

/* init serial */ gd->baudrate = CONFIG_BAUDRATE; diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index adc7673..0fd34a2 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -41,14 +41,14 @@ static inline void NF_Conf(u16 conf) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- nand->NFCONF = conf; + writel(conf, &nand->nfconf); }

static inline void NF_Cmd(u8 cmd) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- nand->NFCMD = cmd; + writel(cmd, &nand->nfcmd); }

static inline void NF_CmdW(u8 cmd) @@ -61,7 +61,7 @@ static inline void NF_Addr(u8 addr) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- nand->NFADDR = addr; + writel(addr, &nand->nfaddr); }

static inline void NF_SetCE(NFCE_STATE s) @@ -70,10 +70,10 @@ static inline void NF_SetCE(NFCE_STATE s)

switch (s) { case NFCE_LOW: - nand->NFCONF &= ~(1 << 11); + writel(readl(&nand->nfconf) & ~(1 << 11), &nand->nfconf); break; case NFCE_HIGH: - nand->NFCONF |= (1 << 11); + writel(readl(&nand->nfconf) | (1 << 11), &nand->nfconf); break; } } @@ -82,7 +82,7 @@ static inline void NF_WaitRB(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- while (!(nand->NFSTAT & (1 << 0))) + while (!(readl(&nand->nfstat) & (1 << 0))) /* Wait */; }

@@ -90,28 +90,28 @@ static inline void NF_Write(u8 data) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- nand->NFDATA = data; + writeb(data, &nand->nfdata); }

static inline u8 NF_Read(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- return (nand->NFDATA); + return readb(&nand->nfdata); }

static inline void NF_Init_ECC(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- nand->NFCONF |= (1 << 12); + writel(readl(&nand->nfconf) | (1 << 12), &nand->nfconf); }

static inline u32 NF_Read_ECC(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand();

- return (nand->NFECC); + return readl(&nand->nfecc); }

#endif diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index a1b0e0c..8f2da3a 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -47,30 +48,30 @@ int board_init(void)

/* memory and cpu-speed are setup before relocation */ /* change the clock to be 50 MHz 1:1:1 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - gpio->PECON = 0x0; - gpio->PEUP = 0x0; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); + writel(0x0, &gpio->pecon); + writel(0x0, &gpio->peup); #ifdef CONFIG_HWFLOW /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0xa22; + writel(0xa22, &gpio->pfcon); /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->PFUP = 0x35; + writel(0x35, &gpio->pfup); #else /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0x22; + writel(0x22, &gpio->pfcon); /* Disable pull-up on Rx and Tx pins */ - gpio->PFUP = 0x5; + writel(0x5, &gpio->pfup); #endif /* CONFIG_HWFLOW */ - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr);

/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index e3a4490..7b64408 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -72,36 +73,37 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime);

/* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);

/* some delay between MPLL and UPLL */ delay(4000);

/* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon);

/* some delay between MPLL and UPLL */ delay(8000);

/* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044555; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FFBA; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x002AFAAA; - gpio->GPHUP = 0x000007FF; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044555, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FFBA, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x002AFAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup);

/* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 548852f..744bd63 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -31,6 +31,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h>

#if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand.h> @@ -80,40 +81,41 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime);

/* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);

/* some delay between MPLL and UPLL */ delay(4000);

/* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon);

/* some delay between MPLL and UPLL */ delay(8000);

/* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044556; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FF3A; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x0016FAAA; - gpio->GPHUP = 0x000007FF; - - gpio->EXTINT0 = 0x22222222; - gpio->EXTINT1 = 0x22222222; - gpio->EXTINT2 = 0x22222222; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044556, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FF3A, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x0016FAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); + + writel(0x22222222, &gpio->extint0); + writel(0x22222222, &gpio->extint1); + writel(0x22222222, &gpio->extint2);

/* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 4f30c23..27507ec 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -31,6 +31,7 @@ #include <i2c.h> #include <flash.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "trab.h"

diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index 2c31d50..5d686fe 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -26,6 +26,7 @@ #include <common.h> #include <command.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <rtc.h> #include <i2c.h> #include "tsc2000.h" @@ -604,28 +605,33 @@ static int adc_read(unsigned int channel)

adc_init();

- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon);

while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); }

if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; }

- result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF;

- padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon);

debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result);

/* * Wait for ADC to be ready for next conversion. This delay value was @@ -642,8 +648,10 @@ static void adc_init(void)

padc = s3c2400_get_base_adc();

- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon);

/* * Wait some time to avoid problem with very first call of @@ -664,10 +672,10 @@ static void led_set(unsigned int state)

switch (state) { case 0: /* turn LED off */ - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); break; case 1: /* turn LED on */ - gpio->PADAT &= ~(1 << 12); + writel(readl(&gpio->padat) & ~(1 << 12), &gpio->padat); break; default: break; @@ -693,8 +701,8 @@ static void led_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* configure GPA12 as output and set to High -> LED off */ - gpio->PACON &= ~(1 << 12); - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->pacon) & ~(1 << 12), &gpio->pacon); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); }

static void sdelay(unsigned long seconds) diff --git a/board/trab/rs485.c b/board/trab/rs485.c index 79f8cc4..794b197 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -23,6 +23,7 @@

#include <common.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "rs485.h"

static void rs485_setbrg(void); @@ -51,16 +52,16 @@ static void rs485_setbrg(void) reg = (33000000 / (16 * 38400)) - 1;

/* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - uart->UCON = 0x245; - uart->UBRDIV = reg; + writel(0x245, &uart->ucon); + writel(reg, &uart->ubrdiv);

for (i = 0; i < 100; i++) ; @@ -70,16 +71,21 @@ static void rs485_cfgio(void) { struct s3c24x0_gpio *const gpio = s3c24x0_get_base_gpio();

- gpio->PFCON &= ~(0x3 << 2); - gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) & ~(0x3 << 2), &gpio->pfcon); + /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 2), &gpio->pfcon);

- gpio->PFCON &= ~(0x3 << 6); - gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) &= ~(0x3 << 6), &gpio->pfcon); + /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 6), &gpio->pfcon);

- gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ - gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ + /* disable pullup on GPF1 */ + writel(readl(&gpio->pfup) | (1 << 1), &gpio->pfup); + /* disable pullup on GPF3 */ + writel(readl(&gpio->pfup) | (1 << 3), &gpio->pfup);

- gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ + /* set GPA11 (RS485_DE) to output */ + writel(readl(&gpio->pacon) & ~(1 << 11), &gpio->pacon); }

/* @@ -104,10 +110,10 @@ int rs485_getc(void) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);

- while (!(uart->UTRSTAT & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */;

- return uart->URXH & 0xff; + return readl(&uart->urxh) & 0xff; }

/* @@ -117,10 +123,10 @@ void rs485_putc(const char c) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);

- while (!(uart->UTRSTAT & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */;

- uart->UTXH = c; + writeb(c, &uart->utxh);

/* If \n, also do \r */ if (c == '\n') @@ -134,7 +140,7 @@ int rs485_tstc(void) { struct s3c24x0_uart *const uart = s3c24x0_get_base_uart(UART_NR);

- return uart->UTRSTAT & 0x1; + return readl(&uart->utrstat) & 0x1; }

void rs485_puts(const char *s) @@ -171,9 +177,9 @@ static void set_rs485de(unsigned char rs485de_state)

/* This is on PORT A bit 11 */ if (rs485de_state) - gpio->PADAT |= (1 << 11); + writel(readl(&gpio->padat) | (1 << 11), &gpio->padat); else - gpio->PADAT &= ~(1 << 11); + writel(readl(&gpio->padat) & ~(1 << 11), &gpio->padat); }

void trab_rs485_enable_tx(void) diff --git a/board/trab/trab.c b/board/trab/trab.c index 80016bc..d339d07 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <malloc.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <command.h> #include "trab.h"

@@ -74,38 +75,38 @@ int board_init() #ifdef CONFIG_TRAB_50MHZ /* change the clock to be 50 MHz 1:1:1 */ /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); #else /* change the clock to be 133 MHz 1:2:4 */ /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->MPLLCON = 0x7d041; - clk_power->CLKDIVN = 3; + writel(0x7d041, &clk_power->mpllcon); + writel(3, &clk_power->clkdivn); #endif

/* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->PFCON = (2 << 0) | (2 << 2) | (2 << 4) | - (2 << 6) | (2 << 8) | (2 << 10); + writel((2 << 0) | (2 << 2) | (2 << 4) | (2 << 6) | (2 << 8) | (2 << 10), + &gpio->pfcon); #ifdef CONFIG_HWFLOW /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | - (1 << 3) | (1 << 4) | (1 << 5); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5), + &gpio->pfup); #else /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), &gpio->pfup); #endif - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr);

/* suppress flicker of the VFDs */ - gpio->MISCCR = 0x40; - gpio->PFCON |= (2 << 12); + writel(0x40, gpio->misccr); + writel(readl(&gpio->pfcon) | (2 << 12), &gpio->pfcon);

gd->bd->bi_arch_number = MACH_TYPE_TRAB;

@@ -113,8 +114,8 @@ int board_init() gd->bd->bi_boot_params = 0x0c000100;

/* Make sure both buzzers are turned off */ - gpio->PDCON |= 0x5400; - gpio->PDDAT &= ~0xE0; + writel(readl(&gpio->pdcon) | 0x5400, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0xE0, &gpio->pddat);

#ifdef CONFIG_VFD vfd_init_clocks(); @@ -131,7 +132,7 @@ int board_init()

#ifdef CONFIG_DRIVER_S3C24X0_I2C /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; + writel((readl(&gpio->pgcon) & 0x003c00) | 0x003c00, &gpio->pgcon); #endif /* CONFIG_DRIVER_S3C24X0_I2C */

return 0; @@ -328,14 +329,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

- gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); }

static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

- gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); }

static void spi_init(void) @@ -345,23 +346,23 @@ static void spi_init(void) int i;

/* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon);

CLR_CS_TOUCH();

/* Baudrate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon);

/* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); wait_transmit_done(); }

@@ -369,7 +370,7 @@ static void wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();

- while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; }

@@ -384,13 +385,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg, command |= (page << 11); command |= (reg << 5);

- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writel((data & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writel(data & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done();

CLR_CS_TOUCH(); diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index da0c3b1..4708105 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -27,6 +27,7 @@ #include <exports.h> #include <timestamp.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "rs485.h"

@@ -376,28 +377,33 @@ static int adc_read(unsigned int channel) padc = s3c2400_get_base_adc(); channel &= 0x7;

- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon);

while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); }

if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; }

- result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF;

- padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon);

debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result);

/* * Wait for ADC to be ready for next conversion. This delay value was @@ -414,8 +420,10 @@ static void adc_init(void)

padc = s3c2400_get_base_adc();

- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon);

/* * Wait some time to avoid problem with very first call of @@ -456,10 +464,10 @@ int do_power_switch(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* configure GPE7 as input */ - gpio->PECON &= ~(0x3 << (2 * 7)); + writel(readl(&gpio->pecon) & ~(0x3 << (2 * 7)), &gpio->pecon);

/* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; + result = ((readl(&gpio->pedat) & (1 << 7)) == (1 << 7)) ? 0 : 1;

print_identifier(); printf("%d\n", result); @@ -522,20 +530,20 @@ int do_vfd_id(void)

/* try to red vfd board id from the value defined by pull-ups */

- pcup_old = gpio->PCUP; - pccon_old = gpio->PCCON; + pcup_old = readl(&gpio->pcup); + pccon_old = readl(&gpio->pccon);

/* activate GPC0...GPC3 pull-ups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon);

udelay(10); /* allow signals to settle */ /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F;

- gpio->PCCON = pccon_old; - gpio->PCUP = pcup_old; + writel(pccon_old, &gpio->pccon); + writel(pcup_old, &gpio->pcup);

/* print vfd_board_id to console */ print_identifier(); @@ -557,40 +565,42 @@ int do_buzzer(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0);

/* set divider for timer 2 */ - timers->TCFG1 &= ~0xF00; - timers->TCFG1 |= 0x300; + writel(readl(&timers->tcfg1) & ~0xF00, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x300, &timers->tcfg1);

/* set frequency */ counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].TCNTB = counter; - timers->ch[2].TCMPB = counter / 2; + writel(counter, &timers->ch[2].tcntb); + writel(counter / 2, &timers->ch[2].tcmpb);

if (strcmp(argv[2], "on") == 0) { debug("%s: frequency: %d\n", __FUNCTION__, BUZZER_FREQ);

/* configure pin GPD7 as TOUT2 */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x8000; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x8000, &gpio->pdcon);

/* start */ - timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & - ~INVERT2; - timers->TCON = (timers->TCON | START2) & ~UPDATE2; + writel((readl(&timers->tcon) | UPDATE2 | RELOAD2) & ~INVERT2, + &timers->tcon); + writel((readl(&timers->tcon) | START2) & ~UPDATE2, + &timers->tcon); return 0; } else if (strcmp(argv[2], "off") == 0) { /* stop */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon);

/* configure GPD7 as output and set to low */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x4000; - gpio->PDDAT &= ~0x80; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x4000, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0x80, &gpio->pddat); return 0; }

@@ -603,12 +613,12 @@ int do_led(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* configure PC14 and PC15 as output */ - gpio->PCCON &= ~(0xF << 28); - gpio->PCCON |= (0x5 << 28); + writel(readl(&gpio->pccon) & ~(0xF << 28), &gpio->pccon); + writel(readl(&gpio->pccon) | (0x5 << 28), &gpio->pccon);

/* configure PD0 and PD4 as output */ - gpio->PDCON &= ~((0x3 << 8) | 0x3); - gpio->PDCON |= ((0x1 << 8) | 0x1); + writel(readl(&gpio->pdcon) & ~((0x3 << 8) | 0x3), &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 8) | 0x1), &gpio->pdcon);

switch (simple_strtoul(argv[2], NULL, 10)) { case 0: @@ -616,27 +626,27 @@ int do_led(char **argv) break; case 2: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 14); + writel(readl(&gpio->pcdat) | (1 << 14), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 14); + writel(readl(&gpio->pcdat) & ~(1 << 14), &gpio->pcdat); return 0; case 3: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 15); + writel(readl(&gpio->pcdat) | (1 << 15), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 15); + writel(readl(&gpio->pcdat) & ~(1 << 15), &gpio->pcdat); return 0; case 4: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 0); + writel(readl(&gpio->pddat) | (1 << 0), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 0); + writel(readl(&gpio->pddat) & ~(1 << 0), &gpio->pddat); return 0; case 5: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 4); + writel(readl(&gpio->pddat) | (1 << 4), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 4); + writel(readl(&gpio->pddat) & ~(1 << 4), &gpio->pddat); return 0; default: break; @@ -650,22 +660,24 @@ int do_full_bridge(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* configure PD5 and PD6 as output */ - gpio->PDCON &= ~((0x3 << 5 * 2) | (0x3 << 6 * 2)); - gpio->PDCON |= ((0x1 << 5 * 2) | (0x1 << 6 * 2)); + writel(readl(&gpio->pdcon) & ~((0x3 << 5 * 2) | (0x3 << 6 * 2)), + &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 5 * 2) | (0x1 << 6 * 2)), + &gpio->pdcon);

if (strcmp(argv[2], "+") == 0) { - gpio->PDDAT |= (1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) | (1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "-") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "off") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT &= ~(1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) & ~(1 << 6), &gpio->pddat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -755,15 +767,15 @@ int do_motor(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* Configure I/O port */ - gpio->PGCON &= ~(0x3 << 0); - gpio->PGCON |= (0x1 << 0); + writel(readl(&gpio->pgcon) & ~(0x3 << 0), &gpio->pgcon); + writel(readl(&gpio->pgcon) | (0x1 << 0), &gpio->pgcon);

if (strcmp(argv[2], "on") == 0) { - gpio->PGDAT &= ~(1 << 0); + writel(readl(&gpio->pgdat) & ~(1 << 0), &gpio->pgdat); return 0; } if (strcmp(argv[2], "off") == 0) { - gpio->PGDAT |= (1 << 0); + writel(readl(&gpio->pgdat) | (1 << 0), &gpio->pgdat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -783,36 +795,39 @@ int do_pwm(char **argv)

if (strcmp(argv[2], "on") == 0) { /* configure pin GPD8 as TOUT3 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x2 << 8*2); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x2 << 8 * 2), &gpio->pdcon);

/* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0);

/* set divider for timer 3 */ - timers->TCFG1 &= ~(0xf << 12); - timers->TCFG1 |= (0x3 << 12); + writel(readl(&timers->tcfg1) & ~(0xF << 12), &timers->tcfg1); + writel(readl(&timers->tcfg1) | (0x3 << 12), &timers->tcfg1);

/* set frequency */ counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].TCNTB = counter; - timers->ch[3].TCMPB = counter / 2; + writel(counter, &timers->ch[3].tcntb); + writel(counter / 2, &timers->ch[3].tcmpb);

/* start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); return 0; } if (strcmp(argv[2], "off") == 0) {

/* stop timer */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon);

/* configure pin GPD8 as output and set to 0 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x1 << 8*2); - gpio->PDDAT &= ~(1 << 8); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x1 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pddat) & ~(1 << 8), &gpio->pdcon); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index 2855825..c07b4df 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -50,23 +50,23 @@ void tsc2000_spi_init(void) int i;

/* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon);

CLR_CS_TOUCH();

/* Baud-rate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon);

/* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); }

@@ -74,7 +74,7 @@ void spi_wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();

- while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; }

@@ -85,13 +85,13 @@ void tsc2000_write(unsigned short reg, unsigned short data)

SET_CS_TOUCH(); command = reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writeb((data & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writeb(data & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done();

CLR_CS_TOUCH(); @@ -105,19 +105,19 @@ unsigned short tsc2000_read(unsigned short reg) SET_CS_TOUCH(); command = 0x8000 | reg;

- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done();

- spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - data = spi->ch[0].SPRDAT; - spi->ch[0].SPTDAT = 0xFF; + data = readl(&spi->ch[0].sprdat); + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done();

CLR_CS_TOUCH(); - return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); + return (readl(&spi->ch[0].sprdat) & 0x0FF) | (data << 8); }

void tsc2000_set_mux(unsigned int channel) diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h index db4b408..3719c2e 100644 --- a/board/trab/tsc2000.h +++ b/board/trab/tsc2000.h @@ -29,45 +29,75 @@ #define _TSC2000_H_

/* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) - -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) +#define CON_MUX0 (writel((readl(&gpio->pccon) & 0x0FFFFFCFF) | \ + 0x00000100, &gpio->pccon)) +#define CLR_MUX0 (writel(readl(&gpio->pcdat) & 0x0FFEF, \ + &gpio->pcdat)) +#define SET_MUX0 (writel(readl(&gpio->pcdat) | 0x00010, \ + &gpio->pcdat)) + +#define CON_MUX1 (writel((readl(&gpio->pccon) & 0x0FFFFF3FF) | \ + 0x00000400, &gpio->pccon)) +#define CLR_MUX1 (writel(readl(&gpio->pcdat) & 0x0FFDF, \ + &gpio->pcdat)) +#define SET_MUX1 (writel(readl(&gpio->pcdat) | 0x00020, \ + &gpio->pcdat)) + +#define CON_MUX1_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFFCFFF) | \ + 0x00001000, &gpio->pccon)) +#define CLR_MUX1_ENABLE (writel(readl(&gpio->pcdat) | 0x00040, \ + &gpio->pcdat)) +#define SET_MUX1_ENABLE (writel(readl(&gpio->pcdat) & 0x0FFBF, \ + &gpio->pcdat)) + +#define CON_MUX2_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFF3FFF) | \ + 0x00004000, &gpio->pccon)) +#define CLR_MUX2_ENABLE (writel(readl(&gpio->pcdat) | 0x00080, \ + &gpio->pcdat)) +#define SET_MUX2_ENABLE (writel(readl(&gpio->pcdat) & 0x0FF7F, \ + &gpio->pcdat)) + +#define CON_MUX3_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFCFFFF) | \ + 0x00010000, &gpio->pccon)) +#define CLR_MUX3_ENABLE (writel(readl(&gpio->pcdat) | 0x00100, \ + &gpio->pcdat)) +#define SET_MUX3_ENABLE (writel(readl(&gpio->pcdat) & 0x0FEFF, \ + &gpio->pcdat)) + +#define CON_MUX4_ENABLE (writel((readl(&gpio->pccon) & 0x0FFF3FFFF) | \ + 0x00040000, &gpio->pccon)) +#define CLR_MUX4_ENABLE (writel(readl(&gpio->pcdat) | 0x00200, \ + &gpio->pcdat)) +#define SET_MUX4_ENABLE (writel(readl(&gpio->pcdat) & 0x0FDFF, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_0 (writel((readl(&gpio->pccon) & 0x0FFCFFFFF) | \ + 0x00100000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) & 0x0FBFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) | 0x00400, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_1 (writel((readl(&gpio->pccon) & 0x0FF3FFFFF) | \ + 0x00400000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) & 0x0F7FF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) | 0x00800, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_2 (writel((readl(&gpio->pccon) & 0x0FCFFFFFF) | \ + 0x01000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) & 0x0EFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) | 0x01000, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_3 (writel((readl(&gpio->pccon) & 0x0F3FFFFFF) | \ + 0x04000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) & 0x0DFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) | 0x02000, \ + &gpio->pcdat))

/* TSC2000 register definition */ #define TSC2000_REG_X ((0 << 11) | (0 << 5)) @@ -130,14 +160,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

- gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); }

static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

- gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); }

#endif /* _TSC2000_H_ */ diff --git a/board/trab/vfd.c b/board/trab/vfd.c index cc7f9d3..ad5b8c2 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -38,6 +38,7 @@ #include <linux/types.h> #include <stdio_dev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -414,15 +415,15 @@ int vfd_init_clocks(void) * defined by pull-ups */ /* activate GPC0...GPC3 pullups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon); /* allow signals to settle */ /* udelay isn't working yet at this point! */ for (i = 0; i < 10000; i++) __asm__("NOP"); /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F;

VFD_DISABLE; /* activate blank for the vfd */

@@ -434,39 +435,41 @@ int vfd_init_clocks(void) /* Enable 500 Hz timer for fill level sensor to operate * properly */ /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->PDCON &= ~0x30000; - gpio->PDCON |= 0x20000; - gpio->PDUP |= (1 << 8); + writel(readl(&gpio->pdcon) & ~0x30000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x20000, &gpio->pdcon); + writel(readl(&gpio->pdup) | (1 << 8), &gpio->pdup);

/* Configure the prescaler */ - timers->TCFG0 &= ~0xff00; - timers->TCFG0 |= 0x0f00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0);

/* Select MUX input (divider) for timer3 (1/16) */ - timers->TCFG1 &= ~0xf000; - timers->TCFG1 |= 0x3000; + writel(readl(&timers->tcfg1) & ~0xF000, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x3000, &timers->tcfg1);

/* Enable autoreload and set the counter and compare * registers to values for the 500 Hz clock * (for a given prescaler (15) and divider (16)): * counter = (66000000 / 500) >> 9; */ - timers->ch[3].TCNTB = 0x101; - timers->ch[3].TCMPB = 0x101 / 2; + writel(0x101, &timers->ch[3].tcntb); + writel(0x101 / 2, &timers->ch[3].tcmpb);

/* Start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); } #endif /* If old board revision, then use vm-signal as cpld-clock */ - lcd->LCDCON2 = 0x00FFC000; - lcd->LCDCON3 = 0x0007FF00; - lcd->LCDCON4 = 0x00000000; - lcd->LCDCON5 = 0x00000400; - lcd->LCDCON1 = 0x00000B75; + writel(0x00FFC000, &lcd->lcdcon2); + writel(0x0007FF00, &lcd->lcdcon3); + writel(0x00000000, &lcd->lcdcon4); + writel(0x00000400, &lcd->lcdcon5); + writel(0x00000B75, &lcd->lcdcon1); /* VM (GPD1) is used as clock for the CPLD */ - gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; + writel((readl(&gpio->pdcon) & 0xFFFFFFF3) | 0x00000008, &gpio->pdcon);

return 0; } @@ -536,46 +539,46 @@ int drv_vfd_init(void) * see manual S3C2400 */ /* Stopp LCD-Controller */ - lcd->LCDCON1 = 0x00000000; + writel(0x00000000, &lcd->lcdcon1); /* frame buffer startadr */ - lcd->LCDSADDR1 = gd->fb_base >> 1; + writel(gd->fb_base >> 1, &lcd->lcdsaddr1); /* frame buffer endadr */ - lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->LCDSADDR3 = ((256 / 4)); - lcd->LCDCON2 = 0x000DC000; + writel((gd->fb_base + FRAME_BUF_SIZE) >> 1, &lcd->lcdsaddr2); + writel(256 / 4, &lcd->lcdsaddr3); + writel(0x000DC000, &lcd->lcdcon2); if (gd->vfd_type == VFD_TYPE_MN11236) - lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ + writel(37 << 14, &lcd->lcdcon2); /* MN11236: 38 lines */ else - lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ - lcd->LCDCON3 = 0x0051000A; - lcd->LCDCON4 = 0x00000001; + writel(55 << 14, &lcd->lcdcon2); /* T119C: 56 lines */ + writel(0x0051000A, &lcd->lcdcon3); + writel(0x00000001, &lcd->lcdcon4); if (gd->vfd_type && vfd_inv_data) - lcd->LCDCON5 = 0x000004C0; + writel(0x000004C0, &lcd->lcdcon5); else - lcd->LCDCON5 = 0x00000440; + writel(0x00000440, &lcd->lcdcon5);

/* Port pins as LCD output */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00) | 0x000000AA; - gpio->PDCON = (gpio->PDCON & 0xFFFFFF03) | 0x000000A8; + writel((readl(&gpio->pccon) & 0xFFFFFF00) | 0x000000AA, &gpio->pccon); + writel((readl(&gpio->pdcon) & 0xFFFFFF03) | 0x000000A8, &gpio->pdcon);

/* Synchronize VFD enable with LCD controller to avoid flicker */ /* Start LCD-Controller */ - lcd->LCDCON1 = 0x00000B75; - while ((lcd->LCDCON5 & 0x180000) != 0x100000) + writel(0x00000B75, &lcd->lcdcon1); + while ((readl(&lcd->lcdcon5) & 0x180000) != 0x100000) /* Wait for end of VSYNC */; /* Wait for next HSYNC */ - while ((lcd->LCDCON5 & 0x060000) != 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) == 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) == 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) != 0x000000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x000000) ; if (gd->vfd_type) VFD_ENABLE;

- debug("LCDSADDR1: %lX\n", lcd->LCDSADDR1); - debug("LCDSADDR2: %lX\n", lcd->LCDSADDR2); - debug("LCDSADDR3: %lX\n", lcd->LCDSADDR3); + debug("LCDSADDR1: %lX\n", readl(&lcd->lcdsaddr1)); + debug("LCDSADDR2: %lX\n", readl(&lcd->lcdsaddr2)); + debug("LCDSADDR3: %lX\n", readl(&lcd->lcdsaddr3));

return 0; } @@ -589,8 +592,8 @@ void disable_vfd(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

VFD_DISABLE; - gpio->PDCON &= ~0xC; - gpio->PDUP &= ~0x2; + writel(readl(&gpio->pdcon) & ~0xC, &gpio->pdcon); + writel(readl(&gpio->pdup) & ~0x2, &gpio->pdup); }

/************************************************************************/ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 879fda6..5d7b05e 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -33,10 +33,11 @@

#include <asm/arch/s3c24x0_cpu.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h>

void do_irq (struct pt_regs *pt_regs) { struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt(); - u_int32_t intpnd = readl(&irq->INTPND); + u_int32_t intpnd = readl(&irq->intpnd);

} diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index b13283a..58e8865 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s;

if (pllreg == MPLL) - r = readl(&clk_power->MPLLCON); + r = readl(&clk_power->mpllcon); else if (pllreg == UPLL) - r = readl(&clk_power->UPLLCON); + r = readl(&clk_power->upllcon); else hang();

@@ -78,7 +78,7 @@ ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();

- return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); + return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); }

/* return PCLK frequency */ @@ -86,7 +86,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();

- return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); + return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); }

/* return UCLK frequency */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 7d47354..9fcfec2 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers();

- return readl(&timers->TCNTO4) & 0xffff; + return readl(&timers->tcnto4) & 0xffff; }

static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void)

/* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->TCFG0); + writel(0x0f00, &timers->tcfg0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val; - writel(timer_load_val, &timers->TCNTB4); + writel(timer_load_val, &timers->tcntb4); /* auto load, manual update of Timer 4 */ - tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->TCON); + tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; + writel(tmr, &timers->tcon); /* auto load, start Timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->TCON); + writel(tmr, &timers->tcon); timestamp = 0;

return (0); @@ -206,13 +206,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog();

/* Disable watchdog */ - writel(0x0000, &watchdog->WTCON); + writel(0x0000, &watchdog->wtcon);

/* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->WTCNT); + writel(0x0001, &watchdog->wtcnt);

/* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->WTCON); + writel(0x0021, &watchdog->wtcon);

while (1) /* loop forever and wait for reset to happen */; diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index e468ed0..2033965 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,15 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON); + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR); + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);

/* * Enable USB host clock. */ - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);

return 0; } @@ -55,14 +56,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; }

int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; }

diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64..4799610 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,14 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);

/* * Enable USB host clock. */ - clk_power->CLKCON |= (1 << 4); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);

memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1710,8 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; }

@@ -1722,7 +1724,8 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; } #ifdef DEBUG @@ -1748,7 +1751,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; }

diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index e6c0083..4e43344 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -58,10 +58,10 @@ static int get_i2c_sda(void) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();

#ifdef CONFIG_S3C2410 - return (readl(&gpio->GPEDAT) & 0x8000) >> 15; + return (readl(&gpio->gpedat) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (readl(&gpio->PGDAT) & 0x0020) >> 5; + return (readl(&gpio->pgdat) & 0x0020) >> 5; #endif }

@@ -70,10 +70,10 @@ static void set_i2c_scl(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();

#ifdef CONFIG_S3C2410 - writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); + writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 - writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); + writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif }

@@ -83,26 +83,26 @@ static int wait_for_xfer(void) int i;

i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { udelay(100); i--; }

- return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; }

static int is_ack(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();

- return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); }

static void read_write_byte(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();

- writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); + writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); }

void i2c_init(int speed, int slaveadd) @@ -115,30 +115,30 @@ void i2c_init(int speed, int slaveadd) /* wait for some time to give previous transfer a chance to finish */

i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; }

- if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || get_i2c_sda() == 0) { + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || get_i2c_sda() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = readl(&gpio->GPECON); + ulong old_gpecon = readl(&gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = readl(&gpio->PGCON); + ulong old_gpecon = readl(&gpio->pgcon); #endif /* bus still busy probably by (most) previously interrupted transfer */

#ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, - &gpio->GPECON); + writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, + &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, - &gpio->PGCON); + writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, + &gpio->pgcon); #endif

/* toggle I2CSCL until bus idle */ @@ -157,10 +157,10 @@ void i2c_init(int speed, int slaveadd)

/* restore pin functions */ #ifdef CONFIG_S3C2410 - writel(old_gpecon, &gpio->GPECON); + writel(old_gpecon, &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - writel(old_gpecon, &gpio->PGCON); + writel(old_gpecon, &gpio->pgcon); #endif }

@@ -176,13 +176,13 @@ void i2c_init(int speed, int slaveadd)

/* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);

/* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->IICSTAT); - writel(slaveadd, &i2c->IICADD); + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);

}

@@ -211,47 +211,47 @@ int i2c_transfer(unsigned char cmd_type,

/* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; }

- if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) + if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT;

- writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); result = I2C_OK;

switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } } else { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } @@ -261,42 +261,42 @@ int i2c_transfer(unsigned char cmd_type, result = wait_for_xfer();

/* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break;

case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer(); if (is_ack()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); result = wait_for_xfer(); i++; }

- writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->IICSTAT); + I2C_START_STOP, &i2c->iicstat); read_write_byte(); result = wait_for_xfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) - & ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) + & ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -304,11 +304,11 @@ int i2c_transfer(unsigned char cmd_type, }

} else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer();

if (is_ack()) { @@ -316,11 +316,11 @@ int i2c_transfer(unsigned char cmd_type, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) & - ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) & + ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -329,7 +329,7 @@ int i2c_transfer(unsigned char cmd_type, }

/* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break;

diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index a27d47e..ccc771f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W;

if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, + &nand->nfconf); else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, + &nand->nfconf); }

if (cmd != NAND_CMD_NONE) @@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "dev_ready\n"); - return readl(&nand->NFSTAT) & 0x01; + return readl(&nand->nfstat) & 0x01; }

#ifdef CONFIG_S3C2410_NAND_HWECC @@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); }

static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); - ecc_code[0] = readb(&nand->NFECC); - ecc_code[1] = readb(&nand->NFECC + 1); - ecc_code[2] = readb(&nand->NFECC + 2); + ecc_code[0] = readb(&nand->nfecc); + ecc_code[1] = readb(&nand->nfecc + 1); + ecc_code[2] = readb(&nand->nfecc + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]);

@@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand)

debugX(1, "board_nand_init()\n");

- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);

/* initialize hardware */ twrph0 = 3; @@ -141,10 +141,10 @@ int board_nand_init(struct nand_chip *nand) cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + writel(cfg, &nand_reg->nfconf);

/* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata;

nand->select_chip = NULL;

diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 04de5ca..7f02f05 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a)

switch (a) { case RTC_ENABLE: - writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); break;

case RTC_DISABLE: - writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); break; } } @@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp)

/* read RTC registers */ do { - sec = readb(&rtc->BCDSEC); - min = readb(&rtc->BCDMIN); - hour = readb(&rtc->BCDHOUR); - mday = readb(&rtc->BCDDATE); - wday = readb(&rtc->BCDDAY); - mon = readb(&rtc->BCDMON); - year = readb(&rtc->BCDYEAR); - } while (sec != readb(&rtc->BCDSEC)); + sec = readb(&rtc->bcdsec); + min = readb(&rtc->bcdmin); + hour = readb(&rtc->bcdhour); + mday = readb(&rtc->bcddate); + wday = readb(&rtc->bcdday); + mon = readb(&rtc->bcdmon); + year = readb(&rtc->bcdyear); + } while (sec != readb(&rtc->bcdsec));

/* read ALARM registers */ - a_sec = readb(&rtc->ALMSEC); - a_min = readb(&rtc->ALMMIN); - a_hour = readb(&rtc->ALMHOUR); - a_date = readb(&rtc->ALMDATE); - a_mon = readb(&rtc->ALMMON); - a_year = readb(&rtc->ALMYEAR); - a_armed = readb(&rtc->RTCALM); + a_sec = readb(&rtc->almsec); + a_min = readb(&rtc->almmin); + a_hour = readb(&rtc->almhour); + a_date = readb(&rtc->almdate); + a_mon = readb(&rtc->almmon); + a_year = readb(&rtc->almyear); + a_armed = readb(&rtc->rtcalm);

/* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp) SetRTC_Access(RTC_ENABLE);

/* write RTC registers */ - writeb(sec, &rtc->BCDSEC); - writeb(min, &rtc->BCDMIN); - writeb(hour, &rtc->BCDHOUR); - writeb(mday, &rtc->BCDDATE); - writeb(wday, &rtc->BCDDAY); - writeb(mon, &rtc->BCDMON); - writeb(year, &rtc->BCDYEAR); + writeb(sec, &rtc->bcdsec); + writeb(min, &rtc->bcdmin); + writeb(hour, &rtc->bcdhour); + writeb(mday, &rtc->bcddate); + writeb(wday, &rtc->bcdday); + writeb(mon, &rtc->bcdmon); + writeb(year, &rtc->bcdyear);

/* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -163,8 +163,8 @@ void rtc_reset(void) { struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();

- writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); - writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); + writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); + writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); }

#endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 5dd4dd8..a613229 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -100,7 +100,7 @@ void _serial_setbrg(const int dev_index) /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1;

- writel(reg, &uart->UBRDIV); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) /* Delay */ ; } @@ -130,26 +130,26 @@ static int serial_init_dev(const int dev_index) #endif

/* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->UFCON); - writel(0x0, &uart->UMCON); + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon);

/* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ULCON); + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - writel(0x245, &uart->UCON); + writel(0x245, &uart->ucon);

#ifdef CONFIG_HWFLOW - writel(0x1, &uart->UMCON); /* RTS up */ + writel(0x1, &uart->umcon); /* RTS up */ #endif

/* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->UMCON); + writel(0x10, &uart->umcon); #endif _serial_setbrg(dev_index);

@@ -175,10 +175,10 @@ int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);

- while (!(readl(&uart->UTRSTAT) & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */ ;

- return readb(&uart->URXH) & 0xff; + return readb(&uart->urxh) & 0xff; }

#if defined(CONFIG_SERIAL_MULTI) @@ -236,15 +236,15 @@ void _serial_putc(const char c, const int dev_index) return; #endif

- while (!(readl(&uart->UTRSTAT) & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ;

#ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + while (hwflow && !(readl(&uart->umstat) & 0x1)) /* Wait for CTS up */ ; #endif

- writeb(c, &uart->UTXH); + writeb(c, &uart->utxh);

/* If \n, also do \r */ if (c == '\n') @@ -271,7 +271,7 @@ int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);

- return readl(&uart->UTRSTAT) & 0x1; + return readl(&uart->utrstat) & 0x1; }

#if defined(CONFIG_SERIAL_MULTI) diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h index 15f53dd..3481dd6 100644 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -33,12 +33,12 @@

/* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - u32 BWSCON; - u32 BANKCON[8]; - u32 REFRESH; - u32 BANKSIZE; - u32 MRSRB6; - u32 MRSRB7; + u32 bwscon; + u32 bankcon[8]; + u32 refresh; + u32 banksize; + u32 mrsrb6; + u32 mrsrb7; };

@@ -72,34 +72,34 @@ struct s3c24x0_usb_host {

/* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - u32 SRCPND; - u32 INTMOD; - u32 INTMSK; - u32 PRIORITY; - u32 INTPND; - u32 INTOFFSET; + u32 srcpnd; + u32 intmod; + u32 intmsk; + u32 priority; + u32 intpnd; + u32 intoffset; #ifdef CONFIG_S3C2410 - u32 SUBSRCPND; - u32 INTSUBMSK; + u32 subsrcpnd; + u32 intsubmsk; #endif };

/* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - u32 DISRC; + u32 disrc; #ifdef CONFIG_S3C2410 - u32 DISRCC; + u32 disrcc; #endif - u32 DIDST; + u32 didst; #ifdef CONFIG_S3C2410 - u32 DIDSTC; + u32 didstc; #endif - u32 DCON; - u32 DSTAT; - u32 DCSRC; - u32 DCDST; - u32 DMASKTRIG; + u32 dcon; + u32 dstat; + u32 dcsrc; + u32 dcdst; + u32 dmasktrig; #ifdef CONFIG_S3C2400 u32 res[1]; #endif @@ -116,90 +116,90 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - u32 LOCKTIME; - u32 MPLLCON; - u32 UPLLCON; - u32 CLKCON; - u32 CLKSLOW; - u32 CLKDIVN; + u32 locktime; + u32 mpllcon; + u32 upllcon; + u32 clkcon; + u32 clkslow; + u32 clkdivn; };

/* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - u32 LCDCON1; - u32 LCDCON2; - u32 LCDCON3; - u32 LCDCON4; - u32 LCDCON5; - u32 LCDSADDR1; - u32 LCDSADDR2; - u32 LCDSADDR3; - u32 REDLUT; - u32 GREENLUT; - u32 BLUELUT; + u32 lcdcon1; + u32 lcdcon2; + u32 lcdcon3; + u32 lcdcon4; + u32 lcdcon5; + u32 lcdsaddr1; + u32 lcdsaddr2; + u32 lcdsaddr3; + u32 redlut; + u32 greenlut; + u32 bluelut; u32 res[8]; - u32 DITHMODE; - u32 TPAL; + u32 dithmode; + u32 tpal; #ifdef CONFIG_S3C2410 - u32 LCDINTPND; - u32 LCDSRCPND; - u32 LCDINTMSK; - u32 LPCSEL; + u32 lcdintpnd; + u32 lcdsrcpnd; + u32 lcdintmsk; + u32 lpcsel; #endif };

/* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - u32 NFCONF; - u32 NFCMD; - u32 NFADDR; - u32 NFDATA; - u32 NFSTAT; - u32 NFECC; + u32 nfconf; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfstat; + u32 nfecc; };

/* UART (see manual chapter 11) */ struct s3c24x0_uart { - u32 ULCON; - u32 UCON; - u32 UFCON; - u32 UMCON; - u32 UTRSTAT; - u32 UERSTAT; - u32 UFSTAT; - u32 UMSTAT; + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 utrstat; + u32 uerstat; + u32 ufstat; + u32 umstat; #ifdef __BIG_ENDIAN u8 res1[3]; - u8 UTXH; + u8 utxh; u8 res2[3]; - u8 URXH; + u8 urxh; #else /* Little Endian */ - u8 UTXH; + u8 utxh; u8 res1[3]; - u8 URXH; + u8 urxh; u8 res2[3]; #endif - u32 UBRDIV; + u32 ubrdiv; };

/* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - u32 TCNTB; - u32 TCMPB; - u32 TCNTO; + u32 tcntb; + u32 tcmpb; + u32 tcnto; };

struct s3c24x0_timers { - u32 TCFG0; - u32 TCFG1; - u32 TCON; + u32 tcfg0; + u32 tcfg1; + u32 tcon; struct s3c24x0_timer ch[4]; - u32 TCNTB4; - u32 TCNTO4; + u32 tcntb4; + u32 tcnto4; };

@@ -207,9 +207,9 @@ struct s3c24x0_timers { struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN u8 res[3]; - u8 EP_FIFO_REG; + u8 ep_fifo_reg; #else /* little endian */ - u8 EP_FIFO_REG; + u8 ep_fifo_reg; u8 res[3]; #endif }; @@ -217,29 +217,29 @@ struct s3c24x0_usb_dev_fifos { struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res2[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res3[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res4[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res5[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res6[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; #else /* little endian */ - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res1[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res2[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res3[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res4[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res5[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; u8 res6[3]; #endif }; @@ -247,69 +247,69 @@ struct s3c24x0_usb_dev_dmas { struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res2[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res3[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res4[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res5[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res6[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res7[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res8[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res9[3]; - u8 INDEX_REG; + u8 index_reg; u8 res10[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res11[3]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res12[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res13[7]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res14[3]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res15[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res16[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; #else /* little endian */ - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res1[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res2[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res3[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res4[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res5[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res6[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res7[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res8[3]; - u8 INDEX_REG; + u8 index_reg; u8 res9[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res10[7]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res11[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res12[3]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res13[7]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res14[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res15[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; @@ -319,18 +319,18 @@ struct s3c24x0_usb_device {

/* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - u32 WTCON; - u32 WTDAT; - u32 WTCNT; + u32 wtcon; + u32 wtdat; + u32 wtcnt; };

/* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - u32 IICCON; - u32 IICSTAT; - u32 IICADD; - u32 IICDS; + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; };

@@ -338,25 +338,25 @@ struct s3c24x0_i2c { struct s3c24x0_i2s { #ifdef __BIG_ENDIAN u16 res1; - u16 IISCON; + u16 iiscon; u16 res2; - u16 IISMOD; + u16 iismod; u16 res3; - u16 IISPSR; + u16 iispsr; u16 res4; - u16 IISFCON; + u16 iisfcon; u16 res5; - u16 IISFIFO; + u16 iisfifo; #else /* little endian */ - u16 IISCON; + u16 iiscon; u16 res1; - u16 IISMOD; + u16 iismod; u16 res2; - u16 IISPSR; + u16 iispsr; u16 res3; - u16 IISFCON; + u16 iisfcon; u16 res4; - u16 IISFIFO; + u16 iisfifo; u16 res5; #endif }; @@ -365,87 +365,87 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - u32 PACON; - u32 PADAT; + u32 pacon; + u32 padat;

- u32 PBCON; - u32 PBDAT; - u32 PBUP; + u32 pbcon; + u32 pbdat; + u32 pbup;

- u32 PCCON; - u32 PCDAT; - u32 PCUP; + u32 pccon; + u32 pcdat; + u32 pcup;

- u32 PDCON; - u32 PDDAT; - u32 PDUP; + u32 pdcon; + u32 pddat; + u32 pdup;

- u32 PECON; - u32 PEDAT; - u32 PEUP; + u32 pecon; + u32 pedat; + u32 peup;

- u32 PFCON; - u32 PFDAT; - u32 PFUP; + u32 pfcon; + u32 pfdat; + u32 pfup;

- u32 PGCON; - u32 PGDAT; - u32 PGUP; + u32 pgcon; + u32 pgdat; + u32 pgup;

- u32 OPENCR; + u32 opencr;

- u32 MISCCR; - u32 EXTINT; + u32 misccr; + u32 extint; #endif #ifdef CONFIG_S3C2410 - u32 GPACON; - u32 GPADAT; + u32 gpacon; + u32 gpadat; u32 res1[2]; - u32 GPBCON; - u32 GPBDAT; - u32 GPBUP; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; u32 res2; - u32 GPCCON; - u32 GPCDAT; - u32 GPCUP; + u32 gpccon; + u32 gpcdat; + u32 gpcup; u32 res3; - u32 GPDCON; - u32 GPDDAT; - u32 GPDUP; + u32 gpdcon; + u32 gpddat; + u32 gpdup; u32 res4; - u32 GPECON; - u32 GPEDAT; - u32 GPEUP; + u32 gpecon; + u32 gpedat; + u32 gpeup; u32 res5; - u32 GPFCON; - u32 GPFDAT; - u32 GPFUP; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; u32 res6; - u32 GPGCON; - u32 GPGDAT; - u32 GPGUP; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; u32 res7; - u32 GPHCON; - u32 GPHDAT; - u32 GPHUP; + u32 gphcon; + u32 gphdat; + u32 gphup; u32 res8;

- u32 MISCCR; - u32 DCLKCON; - u32 EXTINT0; - u32 EXTINT1; - u32 EXTINT2; - u32 EINTFLT0; - u32 EINTFLT1; - u32 EINTFLT2; - u32 EINTFLT3; - u32 EINTMASK; - u32 EINTPEND; - u32 GSTATUS0; - u32 GSTATUS1; - u32 GSTATUS2; - u32 GSTATUS3; - u32 GSTATUS4; + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; #endif };

@@ -454,74 +454,74 @@ struct s3c24x0_gpio { struct s3c24x0_rtc { #ifdef __BIG_ENDIAN u8 res1[67]; - u8 RTCCON; + u8 rtccon; u8 res2[3]; - u8 TICNT; + u8 ticnt; u8 res3[11]; - u8 RTCALM; + u8 rtcalm; u8 res4[3]; - u8 ALMSEC; + u8 almsec; u8 res5[3]; - u8 ALMMIN; + u8 almmin; u8 res6[3]; - u8 ALMHOUR; + u8 almhour; u8 res7[3]; - u8 ALMDATE; + u8 almdate; u8 res8[3]; - u8 ALMMON; + u8 almmon; u8 res9[3]; - u8 ALMYEAR; + u8 almyear; u8 res10[3]; - u8 RTCRST; + u8 rtcrst; u8 res11[3]; - u8 BCDSEC; + u8 bcdsec; u8 res12[3]; - u8 BCDMIN; + u8 bcdmin; u8 res13[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res14[3]; - u8 BCDDATE; + u8 bcddate; u8 res15[3]; - u8 BCDDAY; + u8 bcdday; u8 res16[3]; - u8 BCDMON; + u8 bcdmon; u8 res17[3]; - u8 BCDYEAR; + u8 bcdyear; #else /* little endian */ u8 res0[64]; - u8 RTCCON; + u8 rtccon; u8 res1[3]; - u8 TICNT; + u8 ticnt; u8 res2[11]; - u8 RTCALM; + u8 rtcalm; u8 res3[3]; - u8 ALMSEC; + u8 almsec; u8 res4[3]; - u8 ALMMIN; + u8 almmin; u8 res5[3]; - u8 ALMHOUR; + u8 almhour; u8 res6[3]; - u8 ALMDATE; + u8 almdate; u8 res7[3]; - u8 ALMMON; + u8 almmon; u8 res8[3]; - u8 ALMYEAR; + u8 almyear; u8 res9[3]; - u8 RTCRST; + u8 rtcrst; u8 res10[3]; - u8 BCDSEC; + u8 bcdsec; u8 res11[3]; - u8 BCDMIN; + u8 bcdmin; u8 res12[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res13[3]; - u8 BCDDATE; + u8 bcddate; u8 res14[3]; - u8 BCDDAY; + u8 bcdday; u8 res15[3]; - u8 BCDMON; + u8 bcdmon; u8 res16[3]; - u8 BCDYEAR; + u8 bcdyear; u8 res17[3]; #endif }; @@ -529,34 +529,34 @@ struct s3c24x0_rtc {

/* ADC (see manual chapter 16) */ struct s3c2400_adc { - u32 ADCCON; - u32 ADCDAT; + u32 adccon; + u32 adcdat; };

/* ADC (see manual chapter 16) */ struct s3c2410_adc { - u32 ADCCON; - u32 ADCTSC; - u32 ADCDLY; - u32 ADCDAT0; - u32 ADCDAT1; + u32 adccon; + u32 adctsc; + u32 adcdly; + u32 adcdat0; + u32 adcdat1; };

/* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - u8 SPCON; + u8 spcon; u8 res1[3]; - u8 SPSTA; + u8 spsta; u8 res2[3]; - u8 SPPIN; + u8 sppin; u8 res3[3]; - u8 SPPRE; + u8 sppre; u8 res4[3]; - u8 SPTDAT; + u8 sptdat; u8 res5[3]; - u8 SPRDAT; + u8 sprdat; u8 res6[3]; u8 res7[16]; }; @@ -570,53 +570,53 @@ struct s3c24x0_spi { struct s3c2400_mmc { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 MMCON; + u8 mmcon; u8 res2[3]; - u8 MMCRR; + u8 mmcrr; u8 res3[3]; - u8 MMFCON; + u8 mmfcon; u8 res4[3]; - u8 MMSTA; + u8 mmsta; u16 res5; - u16 MMFSTA; + u16 mmfsta; u8 res6[3]; - u8 MMPRE; + u8 mmpre; u16 res7; - u16 MMLEN; + u16 mmlen; u8 res8[3]; - u8 MMCR7; - u32 MMRSP[4]; + u8 mmcr7; + u32 mmrsp[4]; u8 res9[3]; - u8 MMCMD0; - u32 MMCMD1; + u8 mmcmd0; + u32 mmcmd1; u16 res10; - u16 MMCR16; + u16 mmcr16; u8 res11[3]; - u8 MMDAT; + u8 mmdat; #else - u8 MMCON; + u8 mmcon; u8 res1[3]; - u8 MMCRR; + u8 mmcrr; u8 res2[3]; - u8 MMFCON; + u8 mmfcon; u8 res3[3]; - u8 MMSTA; + u8 mmsta; u8 res4[3]; - u16 MMFSTA; + u16 mmfsta; u16 res5; - u8 MMPRE; + u8 mmpre; u8 res6[3]; - u16 MMLEN; + u16 mmlen; u16 res7; - u8 MMCR7; + u8 mmcr7; u8 res8[3]; - u32 MMRSP[4]; - u8 MMCMD0; + u32 mmrsp[4]; + u8 mmcmd0; u8 res9[3]; - u32 MMCMD1; - u16 MMCR16; + u32 mmcmd1; + u16 mmcr16; u16 res10; - u8 MMDAT; + u8 mmdat; u8 res11[3]; #endif }; @@ -624,29 +624,29 @@ struct s3c2400_mmc {

/* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - u32 SDICON; - u32 SDIPRE; - u32 SDICARG; - u32 SDICCON; - u32 SDICSTA; - u32 SDIRSP0; - u32 SDIRSP1; - u32 SDIRSP2; - u32 SDIRSP3; - u32 SDIDTIMER; - u32 SDIBSIZE; - u32 SDIDCON; - u32 SDIDCNT; - u32 SDIDSTA; - u32 SDIFSTA; + u32 sdicon; + u32 sdipre; + u32 sdicarg; + u32 sdiccon; + u32 sdicsta; + u32 sdirsp0; + u32 sdirsp1; + u32 sdirsp2; + u32 sdirsp3; + u32 sdidtimer; + u32 sdibsize; + u32 sdidcon; + u32 sdidcnt; + u32 sdidsta; + u32 sdifsta; #ifdef __BIG_ENDIAN u8 res[3]; - u8 SDIDAT; + u8 sdidat; #else - u8 SDIDAT; + u8 sdidat; u8 res[3]; #endif - u32 SDIIMSK; + u32 sdiimsk; };

#endif /*__S3C24X0_H__*/