From: Vaishnav Achath vaishnav.a@ti.com
Add 32-bit address overrides for Hyper Bus Memory Controller for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath vaishnav.a@ti.com Signed-off-by: Anurag Dutta a-dutta@ti.com --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f096b10279..aeb5040a17 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -96,6 +96,13 @@ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; };
+&hbmc { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; + ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, + <0x1 0x0 0x0 0x54000000 0x800000>; +}; + &mcu_ringacc { ti,sci = <&dm_tifs>; };