On 10/9/23 18:46, Paul Barker wrote:
The memory map for the RZ/G2L family differs from that of previous R-Car Gen3/Gen4 SoCs.
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included here (note that this is a 34-bit address space):
- 0x0_0000_0000 - 0x0_0002_FFFF SRAM area
- 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area
- 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area
- 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area
- 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area
- 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB)
- 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware. The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use in TrustedFirmware/OP-TEE, but all other memory is included in the memory map. This reservation is the same as used in R-Car Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs.
Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Reviewed-by: Marek Vasut marek.vasut+renesas@mailbox.org