Re: [U-Boot] TLB mapping for pcie mem space for fsl corenet processors

On 07/04/2013 01:13:29 PM, Sughosh Ganu wrote:

hi, The tlb entries for the pcie mem space for the corenet SoC's is done for 1.5GiB but certain boards use all the 4 pcie controller instantiations, and each controller is assigned 512MiB size in the config files. Should the tlb entries not map 2GiB space as against 1.5GiB. Am i missing something. Thanks.

You'll need to either use a smaller mapping for one or more PCIe controllers, or reduce the amount of RAM you map. There's no room to map 2GiB of RAM, 2GiB of PCIe, *and* CCSR, localbus, etc.

Do you really need to access devices on all four controllers from within U-Boot?

-Scott