On Wednesday, December 02, 2015 at 07:12:50 AM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
v3: remove duplicate reset function use CONFIG_SOCFPGA_GEN5 v2: integrate into a5/c5 reset manager
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@@ -26,13 +28,25 @@ void socfpga_per_reset(u32 reset, int set) if (RSTMGR_BANK(reset) == 0) reg = &reset_manager_base->mpu_mod_reset; else if (RSTMGR_BANK(reset) == 1) +#if defined(CONFIG_SOCFPGA_GEN5) reg = &reset_manager_base->per_mod_reset; +#else
reg = &reset_manager_base->per0_mod_reset;+#endif
The other option would be to just rename these registers for in struct socfpga_reset_manager {} and you won't need those ifdefs.
else if (RSTMGR_BANK(reset) == 2) +#if defined(CONFIG_SOCFPGA_GEN5) reg = &reset_manager_base->per2_mod_reset; +#else
reg = &reset_manager_base->per1_mod_reset;+#endif
Same here.
else if (RSTMGR_BANK(reset) == 3) reg = &reset_manager_base->brg_mod_reset; else if (RSTMGR_BANK(reset) == 4) +#if defined(CONFIG_SOCFPGA_GEN5) reg = &reset_manager_base->misc_mod_reset; +#else
reg = &reset_manager_base->sys_mod_reset;+#endif
I'd just add a comment that misc_mod_reset is sys_mod_reset on gen10 and also rename it.
else /* Invalid reset register, do nothing */ return;
@@ -46,13 +60,29 @@ void socfpga_per_reset(u32 reset, int set)
- Assert reset on every peripheral but L4WD0.
- Watchdog must be kept intact to prevent glitches
- and/or hangs.
- For the Arria10, we disable all the peripherals except L4 watchdog0,
*/
- L4 Timer 0, and ECC.
void socfpga_per_reset_all(void) { +#if defined(CONFIG_SOCFPGA_GEN5) const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
writel(~l4wd0, &reset_manager_base->per_mod_reset); writel(0xffffffff, &reset_manager_base->per2_mod_reset); +#else
- const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));- unsigned mask_ecc_ocp = 0x0000FF00;
- /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
- writel(~l4wd0, &reset_manager_base->per1_mod_reset);
- setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
- /* Finally disable the ECC_OCP */
- setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
+#endif }
/*
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