Currently we may end up with an LCD clock divider that differs from the HDMI PHY clock divider if we can't exactly match the pixel clock. Fix this by using DIV_ROUND_UP to calculate the divider. This works since the PLL is chosen such that the resulting pixel clock is never higher than the requested pixel clock.
Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup")
Signed-off-by: Mark Kettenis kettenis@openbsd.org --- drivers/video/sunxi/sunxi_dw_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index cec23295b5..66a319187c 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -254,7 +254,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - int div = clock_get_pll3() / edid->pixelclock.typ; + int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ); struct sunxi_lcdc_reg *lcdc;
if (mux == 0) {