Hello Leo,
On Tue, May 14, 2013 at 6:53 AM, SARTRE Leo lsartre@adeneo-embedded.com wrote:
Add minimal support (only boot from mmc device) for the Congatec Conga-QEVAl Evaluation Carrier Board with a conga-Qmx6 module.
Signed-off-by: Leo Sartre lsartre@adeneo-embedded.com
Please add Stefano (i.MX custodian) to Cc when sending i.MX patches.
diff --git a/board/congatec/cgtqmx6/Makefile b/board/congatec/cgtqmx6/Makefile
I'd use cgtgmx6eval as it is indeed Carrier Board specific.
...
+++ b/board/congatec/cgtqmx6/README @@ -0,0 +1,28 @@ +U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board
+This file contains information for the port of U-Boot to the Congatec +Conga-QEVAl Evaluation Carrier board.
+1. Boot source, boot from SD card +---------------------------------
+This version of u-boot works only on the SD card. By default, the +Congatec board can boot only from the SPI-NOR. +But, with the u-boot version provided with the board you can write boot +registers to force the board to reboot and boot from the SD slot. If +"bmode" command is not available from your pre-installed u-boot, these +instruction will produce the same effect:
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850 +conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000 +conga-QMX6 U-Boot > reset +resetting ...
+The the board will reboot and, if you burnt your SD correctly the +board will use u-boot that live into the SD
..., if you have written your SD correctly ...
+To copy the resulting u-boot.imx to the SD card:
- sudo dd if=u-boot.imx of=/dev/xxx bs=512 seek=2&&sudo sync
I'd not add 'sudo' prefix. Some people may run it as root already or have given rights to write to the block device. Please remove the '&& sudo sync' from it as well.
+Note: Replace xxx with the device representing the SD card in your system. diff --git a/board/congatec/cgtqmx6/cgtqmx6.c b/board/congatec/cgtqmx6/cgtqmx6.c new file mode 100644 index 0000000..d05d529 --- /dev/null +++ b/board/congatec/cgtqmx6/cgtqmx6.c @@ -0,0 +1,185 @@ +/*
- Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- See file CREDITS for list of people who contributed to this
- project.
- This file is based on mx6qsabrelite.c
- Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- Leo Sartre, lsartre@adeneo-embedded.com
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)+int dram_init(void) +{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);return 0;+}
+iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),+};
+iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),+};
+iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */+};
+static void setup_iomux_uart(void) +{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));+}
+#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},{USDHC4_BASE_ADDR},+};
+int board_mmc_getcd(struct mmc *mmc) +{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;int ret;switch (cfg->esdhc_base) {case USDHC2_BASE_ADDR:gpio_direction_input(IMX_GPIO_NR(1, 4));ret = !gpio_get_value(IMX_GPIO_NR(1, 4));break;case USDHC4_BASE_ADDR:gpio_direction_input(IMX_GPIO_NR(2, 6));ret = !gpio_get_value(IMX_GPIO_NR(2, 6));break;default:printf("Bad USDHC interface\n");}return ret;+}
+int board_mmc_init(bd_t *bis) +{
s32 status = 0;usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |fsl_esdhc_initialize(bis, &usdhc_cfg[1]);return status;+} +#endif
+int board_early_init_f(void) +{
setup_iomux_uart();return 0;+}
+int board_init(void) +{
u32 reg;/*Same init as the sabrelite*/writel(0x41736166, SNVS_BASE_ADDR + 0x64);/*set LPPGDR*/udelay(10);reg = readl(SNVS_BASE_ADDR + 0x4c);reg |= (1 << 3);writel(reg, SNVS_BASE_ADDR + 0x4c);/*clear LPSR*//* address of boot parameters */gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;return 0;+}
+int checkboard(void) +{ +#ifdef CONFIG_MX6
Did you miss MX6Q macro?
puts("Board: Congatec QMX6 Quad\n");+#endif +#ifdef CONFIG_MX6DL
puts("Board: Congatec QMX6 Dual\n");+#endif
return 0;+}
+#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */{"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},{"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},{NULL, 0},+}; +#endif
+int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);+#endif
return 0;+} diff --git a/boards.cfg b/boards.cfg index 5d78064..f909f70 100644 --- a/boards.cfg +++ b/boards.cfg @@ -258,6 +258,7 @@ vision2 arm armv7 vision2 ttcontr mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +cgtqmx6 arm armv7 cgtqmx6 congatec mx6 cgtqmx6:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
I think you missed the MX6Q and MX6DL setting.
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg eco5pk arm armv7 eco5pk 8dtech omap3 nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 diff --git a/include/configs/cgtqmx6.h b/include/configs/cgtqmx6.h new file mode 100644 index 0000000..ce1a9f5 --- /dev/null +++ b/include/configs/cgtqmx6.h @@ -0,1 +1,198 @@ +/*
- cgtqmx6.h
- Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- Congatec Conga-QEVAl board configuration file.
- Based on Freescale i.MX6Q Sabre Lite board configuration file.
- Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- Leo Sartre, lsartre@adeneo-embedded.com
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_MX6 +#define CONFIG_MX6Q
You could pass it in config and allow for Q and DL to share same config and code. Check how Wandboard support has been done for reference.
+#include "mx6_common.h"
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MACH_TYPE 4122
+#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h>
+#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE
+/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION
+/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200
+/* Command definition */ +#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000
+#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \"uimage=uImage\0" \"fdt_file=imx6q-congatec.dtb\0" \"boot_dir=/boot\0" \"console=ttymxc1\0" \"fdt_high=0xffffffff\0" \"initrd_high=0xffffffff\0" \"fdt_addr=0x11000000\0" \"boot_fdt=try\0" \"mmcdev=1\0" \"mmcpart=1\0" \"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \"mmcargs=setenv bootargs console=${console},${baudrate} " \"root=${mmcroot}\0" \"loadbootscript=" \"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \"bootscript=echo Running bootscript from mmc ...; " \"source\0" \"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${boot_dir}/${uimage}\0" \"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${boot_dir}/${fdt_file}\0" \"mmcboot=echo Booting from mmc ...; " \"run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if run loadfdt; then " \"bootm ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootm; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootm; " \"fi;\0"+#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loaduimage; then " \"run mmcboot; " \"else "\"echo ERR: Fail to boot from mmc; " \"fi; " \"fi; " \"else run netboot; fi"
The environment seems heavily based on SabreLITE env. We did some more improvements lately in Wandboard and default environment which you might want to use. Take a look there for reference.
Regards,
-- Otavio Salvador O.S. Systems E-mail: otavio@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br