Hi Fabio,
On 20.08.2014 23:24, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@freescale.com
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Changes since v1:
- Avoid too many ifdef's by providing a dma_rx_align() funtion as suggested
by Otavio
drivers/net/fec_mxc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..1a5105e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000
+#define ARCH_DMA_MINALIGN_MX6SX 64
- #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
@@ -267,6 +269,15 @@ static int fec_tx_task_disable(struct fec_priv *fec) return 0; }
+static int dma_rx_align(void) +{ +#ifdef CONFIG_MX6SX
- return ARCH_DMA_MINALIGN_MX6SX;
+#else
- return ARCH_DMA_MINALIGN;
+#endif
Why don't you just use the bigger value (64) for all SoC versions? Shouldn't hurt, right. And would keep the source clean.
Thanks, Stefan