SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else.
This needs testing on other platforms.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/pci/pci-uclass.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 0756bbe..6dda056 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -674,8 +674,8 @@ static int decode_regions(struct pci_controller *hose, const void *blob, int parent_node, int node) { int pci_addr_cells, addr_cells, size_cells; + phys_addr_t base = 0, addr; int cells_per_record; - phys_addr_t addr; const u32 *prop; int len; int i; @@ -729,8 +729,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob, addr = gd->ram_size; if (gd->pci_ram_top && gd->pci_ram_top < addr) addr = gd->pci_ram_top; - pci_set_region(hose->regions + hose->region_count++, 0, 0, addr, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); +#ifdef CONFIG_SYS_SDRAM_BASE + base = CONFIG_SYS_SDRAM_BASE; +#endif + pci_set_region(hose->regions + hose->region_count++, base, base, + addr, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
return 0; }