On Tue, Oct 25, 2022 at 08:58:46AM +0100, Conor Dooley wrote:
The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change.
As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley conor.dooley@microchip.com
drivers/clk/microchip/mpfs_clk.c | 23 ++++- drivers/clk/microchip/mpfs_clk.h | 8 ++ drivers/clk/microchip/mpfs_clk_msspll.c | 119 ++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com