When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot)
This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20 SoC (Cortex-A72) hangs in U-Boot. The solution I found is to read sctlr_el1 and write back the value as-is. This should be no effect, but surprisingly fixes the problem and LD20 SoC boots. I do not know why.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/arm64/Makefile | 2 ++ arch/arm/mach-uniphier/arm64/lowlevel_init.S | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm/mach-uniphier/arm64/lowlevel_init.S
diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index eb34c20..3fde6b1 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -9,5 +9,7 @@ obj-y += mem_map.o ifdef CONFIG_ARMV8_MULTIENTRY obj-y += smp.o smp_kick_cpus.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o +else +obj-y += lowlevel_init.o endif endif diff --git a/arch/arm/mach-uniphier/arm64/lowlevel_init.S b/arch/arm/mach-uniphier/arm64/lowlevel_init.S new file mode 100644 index 0000000..a4255bf --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + /* + * I do not know why, but LD20 SoC (Cortex-A72) does not work + * without the following code. + */ + mrs x0, sctlr_el1 + msr sctlr_el1, x0 + ret +ENDPROC(lowlevel_init)