Signed-off-by: Stefan Roese sr@denx.de --- v3: - Added USB EHCI support - Added performance enhanced OneNAND read support
v2: - Fixed issues in u-boot.lds mentioned by Andrew Dyer
MAINTAINERS | 4 + MAKEALL | 12 ++ Makefile | 35 ++++ board/micronas/vct/vcth/reg_dcgu.h | 36 ++++ board/micronas/vct/vcth/reg_ebi.h | 242 ++++++++++++++++++++++++++++ board/micronas/vct/vcth/reg_fwsram.h | 73 +++++++++ board/micronas/vct/vcth/reg_gpio.h | 32 ++++ board/micronas/vct/vcth/reg_scc.h | 102 ++++++++++++ board/micronas/vct/vcth/reg_usbh.h | 33 ++++ board/micronas/vct/vcth/reg_wdt.h | 24 +++ board/micronas/vct/vcth2/reg_ebi.h | 290 ++++++++++++++++++++++++++++++++++ board/micronas/vct/vctv/reg_dcgu.h | 25 +++ board/micronas/vct/vctv/reg_ebi.h | 290 ++++++++++++++++++++++++++++++++++ board/micronas/vct/vctv/reg_gpio.h | 32 ++++ board/micronas/vct/vctv/reg_wdt.h | 24 +++ 15 files changed, 1254 insertions(+), 0 deletions(-) create mode 100644 board/micronas/vct/vcth/reg_dcgu.h create mode 100644 board/micronas/vct/vcth/reg_ebi.h create mode 100644 board/micronas/vct/vcth/reg_fwsram.h create mode 100644 board/micronas/vct/vcth/reg_gpio.h create mode 100644 board/micronas/vct/vcth/reg_scc.h create mode 100644 board/micronas/vct/vcth/reg_usbh.h create mode 100644 board/micronas/vct/vcth/reg_wdt.h create mode 100644 board/micronas/vct/vcth2/reg_ebi.h create mode 100644 board/micronas/vct/vctv/reg_dcgu.h create mode 100644 board/micronas/vct/vctv/reg_ebi.h create mode 100644 board/micronas/vct/vctv/reg_gpio.h create mode 100644 board/micronas/vct/vctv/reg_wdt.h
diff --git a/MAINTAINERS b/MAINTAINERS index f048795..5418b6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -659,6 +659,10 @@ Thomas Lange thomas@corelatus.se Vlad Lungu vlad.lungu@windriver.com qemu_mips MIPS32
+Stefan Roese sr@denx.de + + vct_xxx MIPS32 4Kc + ######################################################################### # Nios-32 Systems: # # # diff --git a/MAKEALL b/MAKEALL index cc49a98..ea007cc 100755 --- a/MAKEALL +++ b/MAKEALL @@ -610,6 +610,18 @@ LIST_arm=" \ LIST_mips4kc=" \ incaip \ qemu_mips \ + vct_platinum \ + vct_platinum_small \ + vct_platinum_onenand \ + vct_platinum_onenand_small \ + vct_platinumavc \ + vct_platinumavc_small \ + vct_platinumavc_onenand \ + vct_platinumavc_onenand_small \ + vct_premium \ + vct_premium_small \ + vct_premium_onenand \ + vct_premium_onenand_small \ "
LIST_mips5kc=" \ diff --git a/Makefile b/Makefile index d6cd91a..f2b653c 100644 --- a/Makefile +++ b/Makefile @@ -3000,6 +3000,41 @@ incaip_config: unconfig tb0229_config: unconfig @$(MKCONFIG) $(@:_config=) mips mips tb0229
+vct_premium_config \ +vct_premium_small_config \ +vct_premium_onenand_config \ +vct_premium_onenand_small_config \ +vct_platinum_config \ +vct_platinum_small_config \ +vct_platinum_onenand_config \ +vct_platinum_onenand_small_config \ +vct_platinumavc_config \ +vct_platinumavc_small_config \ +vct_platinumavc_onenand_config \ +vct_platinumavc_onenand_small_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _premium,$@)" ] ; then \ + echo "#define CONFIG_VCT_PREMIUM" > $(obj)include/config.h ; \ + $(XECHO) "... on Premium board variant" ; \ + fi + @if [ "$(findstring _platinum_,$@)" ] ; then \ + echo "#define CONFIG_VCT_PLATINUM" > $(obj)include/config.h ; \ + $(XECHO) "... on Platinum board variant" ; \ + fi + @if [ "$(findstring _platinumavc,$@)" ] ; then \ + echo "#define CONFIG_VCT_PLATINUMAVC" > $(obj)include/config.h ; \ + $(XECHO) "... on PlatinumAVC board variant" ; \ + fi + @if [ "$(findstring _onenand,$@)" ] ; then \ + echo "#define CONFIG_VCT_ONENAND" >> $(obj)include/config.h ; \ + $(XECHO) "... on OneNAND board variant" ; \ + fi + @if [ "$(findstring _small,$@)" ] ; then \ + echo "#define CONFIG_VCT_SMALL_IMAGE" >> $(obj)include/config.h ; \ + $(XECHO) "... stripped down image variant" ; \ + fi + @$(MKCONFIG) -a vct mips mips vct micronas + ######################################################################### ## MIPS32 AU1X00 ######################################################################### diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h new file mode 100644 index 0000000..6ac0ddd --- /dev/null +++ b/board/micronas/vct/vcth/reg_dcgu.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008-2009 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DCGU_BASE 0x00084000 + +/* Relative offsets of the register adresses */ + +#define DCGU_CLK_EN1_OFFS 0x00000010 +#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS) +#define DCGU_CLK_EN2_OFFS 0x00000014 +#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS) +#define DCGU_RESET_UNIT1_OFFS 0x00000018 +#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS) +#define DCGU_USBPHY_STAT_OFFS 0x00000054 +#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS) +#define DCGU_EN_WDT_RESET_OFFS 0x00000064 +#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) + +/* The magic value to write in order to activate the WDT */ +#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h new file mode 100644 index 0000000..7a1e115 --- /dev/null +++ b/board/micronas/vct/vcth/reg_ebi.h @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PREMIUM_H_ +#define _REG_EBI_PREMIUM_H_ + +#define EBI_BASE 0x00000000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000008 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000010 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h new file mode 100644 index 0000000..19afb6b --- /dev/null +++ b/board/micronas/vct/vcth/reg_fwsram.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Premium & Platinum register addresses/definitions seem to be + * identical, so we only need to use one file for both platforms. + */ + +#ifndef _REG_FWSRAM_H_ +#define _REG_FWSRAM_H_ + +#define FWSRAM_BASE 0x00030000 + +/* Relative offsets of the register adresses */ + +#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 +#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) +#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 +#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) +#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 +#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) +#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C +#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) +#define FWSRAM_TOP_CID1_L_OFFS 0x00002010 +#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) +#define FWSRAM_TOP_CID2_H_OFFS 0x00002014 +#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) +#define FWSRAM_TOP_CID2_L_OFFS 0x00002018 +#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) +#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C +#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 +#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 +#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 +#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C +#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 +#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 +#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 +#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C +#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) +#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 +#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) +#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 +#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) +#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 +#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h new file mode 100644 index 0000000..7ada9c9 --- /dev/null +++ b/board/micronas/vct/vcth/reg_gpio.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GPIO1_BASE 0x00088000 +#define GPIO2_BASE 0x0008c000 + +/* Instances */ +#define GPIO_INSTANCES 2 + +/* Relative offsets of the register adresses */ +#define GPIO_SWPORTA_DR_OFFS 0x00000000 +#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) +#define GPIO_SWPORTA_DDR_OFFS 0x00000004 +#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) +#define GPIO_EXT_PORTA_OFFS 0x00000050 +#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vcth/reg_scc.h b/board/micronas/vct/vcth/reg_scc.h new file mode 100644 index 0000000..5e4bfc5 --- /dev/null +++ b/board/micronas/vct/vcth/reg_scc.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2009 Stefan Roese sr@denx.de, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_SCC_PREMIUM_H_ +#define _REG_SCC_PREMIUM_H_ + +#define SCC0_BASE 0x00110000 +#define SCC1_BASE 0x00110080 +#define SCC2_BASE 0x00110100 +#define SCC3_BASE 0x00110180 +#define SCC4_BASE 0x00110200 +#define SCC5_BASE 0x00110280 +#define SCC6_BASE 0x00110300 +#define SCC7_BASE 0x00110380 +#define SCC8_BASE 0x00110400 +#define SCC9_BASE 0x00110480 +#define SCC10_BASE 0x00110500 +#define SCC11_BASE 0x00110580 +#define SCC12_BASE 0x00110600 +#define SCC13_BASE 0x00110680 +#define SCC14_BASE 0x00110700 +#define SCC15_BASE 0x00110780 +#define SCC16_BASE 0x00110800 +#define SCC17_BASE 0x00110880 +#define SCC18_BASE 0x00110900 +#define SCC19_BASE 0x00110980 +#define SCC20_BASE 0x00110a00 +#define SCC21_BASE 0x00110a80 +#define SCC22_BASE 0x00110b00 +#define SCC23_BASE 0x00110b80 +#define SCC24_BASE 0x00110c00 +#define SCC25_BASE 0x00110c80 +#define SCC26_BASE 0x00110d00 +#define SCC27_BASE 0x00110d80 +#define SCC28_BASE 0x00110e00 +#define SCC29_BASE 0x00110e80 +#define SCC30_BASE 0x00110f00 +#define SCC31_BASE 0x00110f80 +#define SCC32_BASE 0x00111000 +#define SCC33_BASE 0x00111080 +#define SCC34_BASE 0x00111100 +#define SCC35_BASE 0x00111180 +#define SCC36_BASE 0x00111200 +#define SCC37_BASE 0x00111280 +#define SCC38_BASE 0x00111300 +#define SCC39_BASE 0x00111380 +#define SCC40_BASE 0x00111400 + +/* Relative offsets of the register adresses */ + +#define SCC_ENABLE_OFFS 0x00000000 +#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) +#define SCC_RESET_OFFS 0x00000004 +#define SCC_RESET(base) ((base) + SCC_RESET_OFFS) +#define SCC_VCID_OFFS 0x00000008 +#define SCC_VCID(base) ((base) + SCC_VCID_OFFS) +#define SCC_MCI_CFG_OFFS 0x0000000C +#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) +#define SCC_PACKET_CFG1_OFFS 0x00000010 +#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) +#define SCC_PACKET_CFG2_OFFS 0x00000014 +#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) +#define SCC_PACKET_CFG3_OFFS 0x00000018 +#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) +#define SCC_DMA_CFG_OFFS 0x0000001C +#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) +#define SCC_CMD_OFFS 0x00000020 +#define SCC_CMD(base) ((base) + SCC_CMD_OFFS) +#define SCC_PRIO_OFFS 0x00000024 +#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) +#define SCC_DEBUG_OFFS 0x00000028 +#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) +#define SCC_STATUS_OFFS 0x0000002C +#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) +#define SCC_IMR_OFFS 0x00000030 +#define SCC_IMR(base) ((base) + SCC_IMR_OFFS) +#define SCC_ISR_OFFS 0x00000034 +#define SCC_ISR(base) ((base) + SCC_ISR_OFFS) +#define SCC_DMA_OFFSET_OFFS 0x00000038 +#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) +#define SCC_RS_CTLSTS_OFFS 0x0000003C +#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_usbh.h b/board/micronas/vct/vcth/reg_usbh.h new file mode 100644 index 0000000..9187a34 --- /dev/null +++ b/board/micronas/vct/vcth/reg_usbh.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2009 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define USBH_BASE 0x00080000 + +/* Relative offsets of the register adresses */ + +#define USBH_CAPLENGTH_OFFS 0x00000100 +#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS) +#define USBH_USBCMD_OFFS 0x00000140 +#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS) +#define USBH_BURSTSIZE_OFFS 0x00000160 +#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS) +#define USBH_USBMODE_OFFS 0x000001A8 +#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS) +#define USBH_USBHMISC_OFFS 0x00000200 +#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS) diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h new file mode 100644 index 0000000..a9b4bf0 --- /dev/null +++ b/board/micronas/vct/vcth/reg_wdt.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define WDT_BASE 0x000b0000 +#define WDT_CR_OFFS 0x00000000 +#define WDT_CR(base) ((base) + WDT_CR_OFFS) +#define WDT_TORR_OFFS 0x00000004 +#define WDT_TORR(base) ((base) + WDT_TORR_OFFS) diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h new file mode 100644 index 0000000..37f0711 --- /dev/null +++ b/board/micronas/vct/vcth2/reg_ebi.h @@ -0,0 +1,290 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PREMIUM_H_ +#define _REG_EBI_PREMIUM_H_ + +#define EBI_BASE 0x00000000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 +#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) +#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C +#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000010 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000018 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_IRQ_MASK2_OFFS 0x0000001C +#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_CRC_GEN_OFFS 0x00000090 +#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_IRQ_STATUS2_OFFS 0x000000B4 +#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) +#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 +#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) +#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 +#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) +#define EBI_ECC0_OFFS 0x000000D0 +#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) +#define EBI_ECC1_OFFS 0x000000D4 +#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) +#define EBI_ECC2_OFFS 0x000000D8 +#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) +#define EBI_ECC3_OFFS 0x000000DC +#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 +#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 +#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) +#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C +#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 +#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 +#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) +#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C +#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 +#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 +#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) +#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C +#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 +#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 +#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) +#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C +#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 +#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h new file mode 100644 index 0000000..6f5c968 --- /dev/null +++ b/board/micronas/vct/vctv/reg_dcgu.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DCGU_BASE 0x0004c000 +#define DCGU_EN_WDT_RESET_OFFS 0x000000FC +#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) + +/* The magic value to write in order to activate the WDT */ +#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h new file mode 100644 index 0000000..82f345e --- /dev/null +++ b/board/micronas/vct/vctv/reg_ebi.h @@ -0,0 +1,290 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PLATINUMAVC_H_ +#define _REG_EBI_PLATINUMAVC_H_ + +#define EBI_BASE 0x00014000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 +#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) +#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C +#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000010 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000018 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_IRQ_MASK2_OFFS 0x0000001C +#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_CRC_GEN_OFFS 0x00000090 +#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_IRQ_STATUS2_OFFS 0x000000B4 +#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) +#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 +#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) +#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 +#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) +#define EBI_ECC0_OFFS 0x000000D0 +#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) +#define EBI_ECC1_OFFS 0x000000D4 +#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) +#define EBI_ECC2_OFFS 0x000000D8 +#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) +#define EBI_ECC3_OFFS 0x000000DC +#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 +#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 +#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) +#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C +#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 +#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 +#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) +#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C +#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 +#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 +#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) +#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C +#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 +#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 +#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) +#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C +#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 +#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h new file mode 100644 index 0000000..24eb8e9 --- /dev/null +++ b/board/micronas/vct/vctv/reg_gpio.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GPIO1_BASE 0x00044000 +#define GPIO2_BASE 0x00048000 + +/* Instances */ +#define GPIO_INSTANCES 2 + +/* Relative offsets of the register adresses */ +#define GPIO_SWPORTA_DR_OFFS 0x00000000 +#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) +#define GPIO_SWPORTA_DDR_OFFS 0x00000004 +#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) +#define GPIO_EXT_PORTA_OFFS 0x00000050 +#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h new file mode 100644 index 0000000..04842e5 --- /dev/null +++ b/board/micronas/vct/vctv/reg_wdt.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2008 Stefan Roese sr@denx.de, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define WDT_BASE 0x00040000 +#define WDT_CR_OFFS 0x00000000 +#define WDT_CR(base) ((base) + WDT_CR_OFFS) +#define WDT_TORR_OFFS 0x00000004 +#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)