On 8/3/07, Ed Swarthout ed.swarthout@hwdebug.com wrote:
From: Ed Swarthout Ed.Swarthout@freescale.com
Only register one miiphy device and attach all phy's to it.
Option CONFIG_TSEC_TBI adds support to configure the internal TBI phy. The first TBI phy address is TBIPA_VALUE=0x11 and incremented for each tsec.
CONFIG_MII_DEFAULT_TSEC will allow any phy connected to the default MII bus to be read or written without being tied to a specific tsec.
Add vsc8234 phy support.
The FSL boards use a sgmii riser card with a 4-port phy at address range 0x1c-0x1f. The CONFIG_SGMII_RISER option adds TSEC1_SGMII_PHY_ADDR_OFFSET to phyaddr when that tsec is configured to sgmii mode by the por config switches.
Ed, I'm sorry but I'm going to have to NACK this, after all.
1) It no longer applies to my tree (not your fault, another patch got in the way)
2) It's far too fragile to have a software requirement that all boards with a TSEC leave 4 consecutive PHY addresses empty. We have boards that put addressable PHYs all around the address space, and it's only a matter of time before a board gets created which breaks this requirement.
3) We have to break out the 8234 support into a separate patch
4) SGMII support should probably *also* be separate
5) I think it's also wrong to assume that all SGMII PHYs will be a simple offset from the normal PHY addresses. Honestly, I believe the common case is that the PHYs will be SGMII or not. Our riser card is probably the exception, rather than the rule, but I feel certain someone will want to put the PHYs at odd addresses in the future. My inclination is still to hard-code the addresses, but I understand why you don't like that idea (and I agree, really).
I think we need to sit down and figure out what the requirements are, and then design a solution to fit those requirements.
Andy