Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede hdegoede@redhat.com --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 3 ++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 +++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 8 +++++ board/sunxi/Kconfig | 2 ++ configs/Mele_M9_defconfig | 3 ++ drivers/usb/host/ehci-sunxi.c | 45 +++++++++++++++++---------- include/configs/sun6i.h | 5 +++ 7 files changed, 61 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 90af8e2..9dca800 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -262,5 +262,8 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) #define CCM_USB_CTRL_PHYGATE (0x1 << 8) +/* These 2 are sun6i only, define them as 0 on sun4i */ +#define CCM_USB_CTRL_PHY1_CLK 0 +#define CCM_USB_CTRL_PHY2_CLK 0
#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 4992dbc..e16a764 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -193,6 +193,10 @@ struct sunxi_ccm_reg {
#define AXI_GATE_OFFSET_DRAM 0
+#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 @@ -205,6 +209,13 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) + #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 6550e50..bdee89e 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -37,16 +37,24 @@ #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_USB0_BASE 0x01c13000 #define SUNXI_USB1_BASE 0x01c14000 +#endif #define SUNXI_SS_BASE 0x01c15000 #define SUNXI_HDMI_BASE 0x01c16000 #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_PATA_BASE 0x01c19000 #define SUNXI_ACE_BASE 0x01c1a000 #define SUNXI_TVE1_BASE 0x01c1b000 #define SUNXI_USB2_BASE 0x01c1c000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b2beea0..c3f865d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -200,6 +200,7 @@ config MMC_SUNXI_SLOT_EXTRA config USB1_VBUS_PIN string "Vbus enable pin for usb1 (ehci0)" default "PH6" if MACH_SUN4I || MACH_SUN7I + default "PH27" if MACH_SUN6I ---help--- Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes a string in the format understood by sunxi_name_to_gpio, e.g. @@ -208,6 +209,7 @@ config USB1_VBUS_PIN config USB2_VBUS_PIN string "Vbus enable pin for usb2 (ehci1)" default "PH3" if MACH_SUN4I || MACH_SUN7I + default "PH24" if MACH_SUN6I ---help--- See USB1_VBUS_PIN help text.
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 3dacb19..f46439f 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -1,4 +1,5 @@ CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" CONFIG_FDTFILE="sun6i-a31-m9.dtb" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y @@ -13,3 +14,5 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb" # HDMI power ? +S:CONFIG_AXP221_ALDO2_VOLT=1800 +S:CONFIG_AXP221_ALDO3_VOLT=3000 +# No Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="" diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 193ac43..cc9a8fa 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -10,16 +10,14 @@ */
#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> #include <asm/gpio.h> #include <asm/io.h> #include <common.h> #include "ehci.h"
-#define SUNXI_USB1_IO_BASE 0x01c14000 -#define SUNXI_USB2_IO_BASE 0x01c1c000 - #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 -#define SUNXI_USB_CSR 0x01c13404 +#define SUNXI_USB_CSR 0x404 #define SUNXI_USB_PASSBY_EN 1
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) @@ -32,23 +30,28 @@ static struct sunxi_ehci_hcd { int usb_rst_mask; int ahb_clk_mask; int gpio_vbus; - void *csr; int irq; int id; } sunxi_echi_hcd[] = { { - .usb_rst_mask = CCM_USB_CTRL_PHY1_RST, + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .csr = (void *)SUNXI_USB_CSR, +#ifndef CONFIG_MACH_SUN6I .irq = 39, +#else + .irq = 72, +#endif .id = 1, }, #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { - .usb_rst_mask = CCM_USB_CTRL_PHY2_RST, + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1, - .csr = (void *)SUNXI_USB_CSR, +#ifndef CONFIG_MACH_SUN6I .irq = 40, +#else + .irq = 74, +#endif .id = 2, } #endif @@ -58,12 +61,16 @@ static int enabled_hcd_count;
static void *get_io_base(int hcd_id) { - if (hcd_id == 1) - return (void *)SUNXI_USB1_IO_BASE; - else if (hcd_id == 2) - return (void *)SUNXI_USB2_IO_BASE; - else + switch (hcd_id) { + case 0: + return (void *)SUNXI_USB0_BASE; + case 1: + return (void *)SUNXI_USB1_BASE; + case 2: + return (void *)SUNXI_USB2_BASE; + default: return NULL; + } }
static int get_vbus_gpio(int hcd_id) @@ -79,7 +86,7 @@ static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr, int data, int len) { int j = 0, usbc_bit = 0; - void *dest = sunxi_ehci->csr; + void *dest = get_io_base(0) + SUNXI_USB_CSR;
usbc_bit = 1 << (sunxi_ehci->id * 2); for (j = 0; j < len; j++) { @@ -112,7 +119,7 @@ static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci) usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
/* threshold adjustment disconnect */ -#ifdef CONFIG_MACH_SUN4I +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I usb_phy_write(sunxi_ehci, 0x2a, 3, 2); #else usb_phy_write(sunxi_ehci, 0x2a, 2, 2); @@ -145,6 +152,9 @@ static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); +#ifdef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask); +#endif
sunxi_usb_phy_init(sunxi_ehci);
@@ -163,6 +173,9 @@ static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
+#ifdef CONFIG_MACH_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask); +#endif clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); } diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 9558771..1b73852 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -18,6 +18,11 @@
#define CONFIG_SYS_PROMPT "sun6i# "
+#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + /* * Include common sunxi configuration where most the settings are */