Hi Lokesh,
Hi Lokesh,
On 23/07/20 2:17 pm, Lokesh Vutla wrote:
Add the basic r5 and a72 basic dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Vishal Mahaveer vishalm@ti.com Signed-off-by: Faiz Abbas faiz_abbas@ti.com
arch/arm/dts/Makefile | 4 +- .../k3-j7200-common-proc-board-u-boot.dtsi | 92 +++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 94 ++++++ arch/arm/dts/k3-j7200-main.dtsi | 313 ++++++++++++++++++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 117 +++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 191 +++++++++++ arch/arm/dts/k3-j7200-som-p0.dtsi | 29 ++ arch/arm/dts/k3-j7200.dtsi | 175 ++++++++++ 8 files changed, 1014 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j7200-common-proc-board.dts create mode 100644 arch/arm/dts/k3-j7200-main.dtsi create mode 100644 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board.dts create mode 100644 arch/arm/dts/k3-j7200-som-p0.dtsi create mode 100644 arch/arm/dts/k3-j7200.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cee10f533f..cdca20206f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -938,7 +938,9 @@ dtb-$(CONFIG_STM32MP15x) += \
...
- main_sdhci0: sdhci@4f8000 {
/s/4f8000/4f80000
compatible = "ti,j7200-sdhci-8bit";
Replace with compatible = "ti,j7200-sdhci-8bit", ti,j721e-sdhci-8bit";
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;clock-names = "clk_xin", "clk_ahb";clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;ti,otap-del-sel-legacy = <0x0>;ti,otap-del-sel-mmc-hs = <0x0>;ti,otap-del-sel-ddr52 = <0x6>;ti,otap-del-sel-hs200 = <0x8>;ti,otap-del-sel-hs400 = <0x0>;ti,strobe-sel = <0x77>;ti,trm-icp = <0x8>;bus-width = <8>;mmc-hs200-1_8v;mmc-ddr-1_8v;dma-coherent;- };
- main_sdhci1: sdhci@4fb000 {
/s/4fb000/4fb0000
compatible = "ti,j7200-sdhci-4bit";
Replace with compatible = "ti,j7200-sdhci-4bit", ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;clock-names = "clk_xin", "clk_ahb";clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;ti,otap-del-sel-legacy = <0x0>;ti,otap-del-sel-sd-hs = <0x0>;ti,otap-del-sel-sdr12 = <0xf>;ti,otap-del-sel-sdr25 = <0xf>;ti,otap-del-sel-sdr50 = <0xc>;ti,otap-del-sel-sdr104 = <0x5>;ti,otap-del-sel-ddr50 = <0xc>;dma-coherent;- };
Thanks, Faiz