
12 Sep
2024
12 Sep
'24
2:40 p.m.
On Tue, Sep 10, 2024 at 7:21 AM Miquel Raynal miquel.raynal@bootlin.com wrote:
/* Make sure bus domain is awake */
ret = power_domain_on(&priv->pd_bus);
if (ret)
return ret;
/* Put devices into reset */
clrbits_le32(priv->base + BLK_SFT_RSTN, reset);
/* Enable upstream clocks */
ret = clk_enable(&priv->clk_apb);
if (ret)
goto dis_bus_pd;
ret = clk_enable(&priv->clk_axi);
if (ret)
goto dis_bus_pd;
/* Enable blk-ctrl clock to allow reset to propagate */
ret = clk_enable(clk);
if (ret)
goto dis_bus_pd;
setbits_le32(priv->base + BLK_CLK_EN, reset);
/* Power up upstream GPC domain */
ret = power_domain_on(domain);
if (ret)
goto dis_bus_pd;
The previously enabled clocks should be disabled on the error paths.
Could you use clk_enable_bulk()?