Hi,
On Tue, Apr 3, 2012 at 3:40 PM, Marek Vasut marex@denx.de wrote:
Mike, there was some issue with this patch?
Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable().
this commit refers to a patch that I sent a while ago as preparation for supporting Lantiq SoCs. Some Lantiq SoCs wants CONF_CM_CACHABLE_NO_WA instead of the hard-coded CONF_CM_CACHABLE_NONCOHERENT. So I created a config option for the required cache mode.
Fix this to avoid inconsistencies if someone wants to disable and enable D-caches.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com
arch/mips/cpu/mips32/cache.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include <asm/addrspace.h> #include <asm/cacheops.h>
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif
#define RA t8
/* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK
- ori t0, CONF_CM_CACHABLE_NONCOHERENT
- ori t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG jr ra END(dcache_enable)
Best regards, Marek Vasut
I only changed start.S and forgot to change this code part too. That is why I created this patch to fix this inconsistency.