Add initial clock driver for Allwinner V3S.
- Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com --- drivers/clk/sunxi/Kconfig | 7 +++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_v3s.c | 51 +++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 drivers/clk/sunxi/clk_v3s.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index c45a4ba378..a6f84e9e56 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -51,6 +51,13 @@ config CLK_SUN8I_R40 This enables common clock driver support for platforms based on Allwinner R40 SoC.
+config CLK_SUN8I_V3S + bool "Clock driver for Allwinner V3S" + default MACH_SUN8I_V3S + help + This enables common clock driver support for platforms based + on Allwinner V3S SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 61f8b87396..fbd43527a6 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o +obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c new file mode 100644 index 0000000000..0eeea84c1a --- /dev/null +++ b/drivers/clk/sunxi/clk_v3s.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-v3s-ccu.h> +#include <dt-bindings/reset/sun8i-v3s-ccu.h> + +static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), +}; + +static struct ccu_reset v3s_resets[] = { + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), +}; + +static const struct ccu_desc v3s_ccu_desc = { + .gates = v3s_gates, + .resets = v3s_resets, +}; + +static int v3s_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 53); +} + +static const struct udevice_id v3s_clk_ids[] = { + { .compatible = "allwinner,sun8i-v3s-ccu", + .data = (ulong)&v3s_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_v3s) = { + .name = "sun8i_v3s_ccu", + .id = UCLASS_CLK, + .of_match = v3s_clk_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = v3s_clk_bind, +};