Hi geniis,
hi,
I notice that in "arch\powerpc\cpu\mpc85xx\cpu_init.c" line 193, version 2010.06:if (! memctl->br1 & 1)
The original intention is to check if V bit of BR1 is set or not, but the operator "!" has higher priority than "&" ,I think it should be changed to:if (! (memctl->br1 & 1))
please check this question, thanks!_______________________________________________
It would have helped if you formulated your inquiry in the form of a patch.
Nevertheless to me it seems like this problem has been fixed in mainline by this commit:
commit f51cdaf19141151ce2b40d562a468605340f2315 Author: Becky Bruce beckyb@kernel.crashing.org Date: Thu Jun 17 11:37:20 2010 -0500
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot.
To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from each processor family.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org Acked-by: Kim Phillips kim.phillips@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
The change includes this code replacement:
+#ifdef CONFIG_MPC85xx + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (get_lbc_br(1) & BR_V) + init_br1 = 0; +#endif
So it does indeed seem to fix the problem you noted.
Cheers Detlev