LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain priyanka.jain@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 19 ++++++++++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 ++++++ 3 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 3274cad..82b7696 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -10,6 +10,8 @@ #include <linux/linkage.h> #include <asm/gic.h> #include <asm/macro.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/soc.h> #ifdef CONFIG_MP #include <asm/arch/mp.h> #endif @@ -137,6 +139,15 @@ ENTRY(lowlevel_init) #endif
#ifdef CONFIG_FSL_TZASC_400 + bl svr_dev_id /* get high 16 bits of SVR */ + /* + * LS2080 and its personalities does not support TZASC + * So skip TZASC related operations + */ + ldr x1, =SVR_DEV_LS2080A + cmp x0, x1 + b.eq 1f + /* Set TZASC so that: * a. We use only Region0 whose global secure write/read is EN * b. We use only Region0 whose NSAID write/read is EN @@ -179,7 +190,7 @@ ENTRY(lowlevel_init) isb dsb sy #endif - +1: #ifdef CONFIG_ARCH_LS1046A /* Initialize the L2 RAM latency */ mrs x1, S3_1_c11_c0_2 @@ -198,6 +209,12 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init)
+svr_dev_id: + ldr x1, =FSL_LSCH3_SVR + ldr w0, [x1] + lsr w0, w0, #16 + ret + #ifdef CONFIG_FSL_LSCH3 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e6cdfcb..1034bf4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) +#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + \ + 0xA4)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) @@ -155,6 +157,7 @@ #define TP_INIT_PER_CLUSTER 4 /* This is chassis generation 3 */
+#ifndef __ASSEMBLY__ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; @@ -320,4 +323,5 @@ struct ccsr_reset {
uint get_svr(void);
+#endif #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 58e90d8..c20fa97 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -31,6 +31,7 @@ #define pex_lut_out32(a, v) out_be32(a, v) #endif
+#ifndef __ASSEMBLY__ struct cpu_type { char name[15]; u32 soc_ver; @@ -39,6 +40,7 @@ struct cpu_type {
#define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} +#endif
#define SVR_WO_E 0xFFFFFE #define SVR_LS1012A 0x870400 @@ -51,6 +53,8 @@ struct cpu_type { #define SVR_LS2085A 0x870100 #define SVR_LS2040A 0x870130
+#define SVR_DEV_LS2080A 0x8701 + #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) @@ -63,6 +67,7 @@ struct cpu_type { #define AHCI_PORT_TRANS_CFG 0x08000029 #define AHCI_PORT_AXICC_CFG 0x3fffffff
+#ifndef __ASSEMBLY__ /* AHCI (sata) register map */ struct ccsr_ahci { u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ @@ -105,4 +110,5 @@ void erratum_a010315(void);
bool soc_has_dp_ddr(void); bool soc_has_aiop(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */