On 9/18/20 4:32 PM, Stefano Babic wrote:
On 18.09.20 16:27, Marek Vasut wrote:
On 9/18/20 4:26 PM, sbabic@denx.de wrote:
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut marex@denx.de Cc: Eric Nelson eric@nelint.com Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Stefano Babic sbabic@denx.de Reviewed-by: Fabio Estevam festevam@gmail.com
Applied to u-boot-imx, master, thanks !
I am tempted to say this should go into next, so it gets really really tested.
So you prefer to drop this ? I mean, we have still a little time, and I am ready to revert it if someone raises his hand. Else it is not bad to have this early in.
I'll leave it up to you.