29 Apr
2008
29 Apr
'08
9:40 p.m.
On Tue, Apr 29, 2008 at 12:18 PM, Andre Schwarz andre.schwarz@matrix-vision.de wrote:
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre Schwarz andre.schwarz@matrix-vision.de
Acked-by: Andy Fleming afleming@freescale.com