DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2 [1].
[1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor b-kapoor@ti.com --- arch/arm/dts/k3-j721s2-main.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 084f8f5b66..8a86f6ce8e 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -766,6 +766,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent;